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Low-power design of an ALU
Title
Low-power design of an ALU.
Creator
Agarwal, Ankur, Florida Atlantic University, Pandya, Abhijit S.
Abstract/Description
There is a mushrooming demand for battery operated applications that require intensive computation in portable environments. This has motivated the research and development of techniques that reduce power in CMOS digital circuits while maintaining their computational throughput. The two essentials to achieve a low power design are miniaturization and long battery life. Lowering the supply voltage is one of the most effective ways to achieve low-power performance as power dissipation in...
Show moreThere is a mushrooming demand for battery operated applications that require intensive computation in portable environments. This has motivated the research and development of techniques that reduce power in CMOS digital circuits while maintaining their computational throughput. The two essentials to achieve a low power design are miniaturization and long battery life. Lowering the supply voltage is one of the most effective ways to achieve low-power performance as power dissipation in digital CMOS circuits is approximately proportional to the square of supply voltage. The basic idea behind this thesis is that it proposes new designs of transfer gate based logical circuits, which use lower supply voltage and less number of transistors than the conventional designs. This work evaluates the obtained results from the proposed designs of the low-power ALU with that from the standard CMOS, other low power designs namely, Wang's XOR, XNOR and Inverter based gates. It was observed that the proposed designs perform better in terms of power consumption than the standard CMOS designs, and the other low power designs mentioned above.
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Date Issued
2003
PURL
http://purl.flvc.org/fcla/dt/13017
Subject Headings
Metal oxide semiconductors, Complementary, Low voltage integrated circuits, Verilog (Computer hardware description language), Logic design
Format
Document (PDF)
Highly scalable multiplier
Title
Highly scalable multiplier.
Creator
Ajmera, Abhijit M., Florida Atlantic University, Shankar, Ravi
Abstract/Description
High speed low power scalable multiplier is needed in computation intensive DSP applications such as video and image compression algorithms. We used an algorithm that folds the larger bit-width operands so smaller bit-width multipliers can be used. Successive folding on operands can be done until a desired threshold is reached. This method has inherent advantages of reuse of optimized building blocks, dynamic reconfiguration, and low power. We implemented a hardware multiplier based on this...
Show moreHigh speed low power scalable multiplier is needed in computation intensive DSP applications such as video and image compression algorithms. We used an algorithm that folds the larger bit-width operands so smaller bit-width multipliers can be used. Successive folding on operands can be done until a desired threshold is reached. This method has inherent advantages of reuse of optimized building blocks, dynamic reconfiguration, and low power. We implemented a hardware multiplier based on this algorithm using Verilog hardware description language. Our results show that this multiplier exhibited significant power advantage over Array and Wallace Tree multipliers for comparable speeds, but had higher gate counts.
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Date Issued
2003
PURL
http://purl.flvc.org/fcla/dt/13080
Subject Headings
Digital multipliers--Design and construction, Multipliers (Mathematical analysis), Verilog (Computer hardware description language)
Format
Document (PDF)
Smart low power obstacle avoidance device
Title
Smart low power obstacle avoidance device.
Creator
Cividanes, Ernesto., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description
Several technologies are being made available for the blind and the visually impaired with the use of infrared and sonar sensors, Radio Frequency Identification, GPS, Wi-Fi among others. Current technologies utilizing microprocessors increase the device's power consumption. In this project, a Verilog Hardware Language (VHDL) designed handheld device that autonomously guides a visually impaired user through an obstacle free path is proposed. The goal is to minimize power consumption by not...
Show moreSeveral technologies are being made available for the blind and the visually impaired with the use of infrared and sonar sensors, Radio Frequency Identification, GPS, Wi-Fi among others. Current technologies utilizing microprocessors increase the device's power consumption. In this project, a Verilog Hardware Language (VHDL) designed handheld device that autonomously guides a visually impaired user through an obstacle free path is proposed. The goal is to minimize power consumption by not using the usual microcontroller and replacing it with components that can increase its speed. Utilizing six infrared sensors, the handheld device is modeled after current technologies which use IR and sonar sensors which are reviewed in this project. By using behavioral modeling, an algorithm for obstacle avoidance and the generation of the obstacle free path is reduced using a K-map and implemented using a multiplexer.
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Date Issued
2010
PURL
http://purl.flvc.org/FAU/2954841
Subject Headings
Verilog (Computer hardware description language), VHDL (Computer hardware description language), Rapid prototyping, Logic design, Intelligent control systems, Brain-computer interfaces
Format
Document (PDF)
low power and high performance centralized full adder
Title
A low power and high performance centralized full adder.
Creator
Srivastav, Sidharth., Florida Atlantic University, Pandya, Abhijit S., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description
In this thesis, we proposed a low power and high performance architecture for 1-bit full adder design. The proposed architecture was proven to offer a wide range of performance ability in terms of power consumption and speed. We implemented the architecture using a 2-input 2 multiplexers, an XOR and an XNOR gate. The proposed architecture and the Standard full adder were designed and simulated using Lasi, Winspice and Silos. Silos, a logic simulation environment was used in the design and...
Show moreIn this thesis, we proposed a low power and high performance architecture for 1-bit full adder design. The proposed architecture was proven to offer a wide range of performance ability in terms of power consumption and speed. We implemented the architecture using a 2-input 2 multiplexers, an XOR and an XNOR gate. The proposed architecture and the Standard full adder were designed and simulated using Lasi, Winspice and Silos. Silos, a logic simulation environment was used in the design and verification of the proposed architecture and the standard full adder that were modeled with Verilog hardware description language. Lasi was used for the layout design of the proposed architecture and the standard full adder. After the layout, both the architectures were compiled separately using LASICKT and a corresponding .CIR file was generated. The .CIR file was imported and executed into WINSPICE3 for the simulation of the circuit.
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Date Issued
2004
PURL
http://purl.flvc.org/fcla/dt/13188
Subject Headings
Digital integrated circuits, Metal oxide semiconductors, Complementary, Integrated circuits--Design and contruction, Verilog (Computer hardware description language), Mixed signal circuits--Design and construction--Computer-aided design
Format
Document (PDF)