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VLSI implementable handwritten digit recognition system using artificial neural networks
Title
A VLSI implementable handwritten digit recognition system using artificial neural networks.
Creator
Agba, Lawrence C., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description
A VLSI implementable feature extraction scheme, and two VLSI implementable algorithms for feature classification that should lead to a practical handwritten digit recognition system are proposed. The feature extraction algorithm exploits the concept of holon dynamics. Holons can be regarded as a group of cooperative processors with self-organizing property. Two types of artificial neural network-based classifiers have been evolved to classify these features. The United States Post Office...
Show moreA VLSI implementable feature extraction scheme, and two VLSI implementable algorithms for feature classification that should lead to a practical handwritten digit recognition system are proposed. The feature extraction algorithm exploits the concept of holon dynamics. Holons can be regarded as a group of cooperative processors with self-organizing property. Two types of artificial neural network-based classifiers have been evolved to classify these features. The United States Post Office handwritten digit database was used to train and test these networks. The first type of classifier system used limited interconnect multi-layer perceptron (LIMP) modules in a hierarchical configuration. Each classifier in this system was independently trained and designated to recognize a particular digit. A maximum of sixty-one digits were used to train and 464 digits which included the training set were used to test the classifiers. A cumulative performance of 93.75% (correctly recognized digits) was recorded. The second classifier system consists of a cluster of small multi-layer perceptron (CLUMP) networks. Each cell in this system was independently trained to trace the boundary between two or more digits in the recognition plane. A combination of these cells distinguish a digit from the rest. This system was trained with 1796 digits and tested on 1918 different set of digits. On the training set a performance of 95.55% was recorded while 79.35% resulted from the test data. These results, which are expected to further improve, are superior to those obtained by other researchers on the same database. This technique of digit recognition is general enough for application in the development of a universal alphanumeric recognition system. A hybrid VLSI system consisting of both analog and digital circuitry, and utilizing both Bi-CMOS and switched capacitor technologies has been designed. The design is intended for implementation with the current MOSIS 2 $\mu$m, double poly, double metal, and p-well CMOS technology. The integrated circuit is such that both classifier systems can be realized using the same chip.
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Date Issued
1990
PURL
http://purl.flvc.org/fcla/dt/12260
Subject Headings
Optical character recognition devices--Computer simulation, Pattern recognition systems--Computer simulation
Format
Document (PDF)
Feature extraction implementation for handwritten numeral recognition
Title
Feature extraction implementation for handwritten numeral recognition.
Creator
Banuru, Prashanth K., Florida Atlantic University, Shankar, Ravi
Abstract/Description
Feature extraction for handwritten character recognition has always been a challenging problem for investigators in the field. The problem gets worse due to large variations present for each type of input character. Our algorithm computes directional features for alphanumeric input mapped on to a hexagonal lattice. The algorithm implements size and scale invariance that is a requirement for achieving a reasonably good recognition rate. Functional performance has been verified for an hexagonal...
Show moreFeature extraction for handwritten character recognition has always been a challenging problem for investigators in the field. The problem gets worse due to large variations present for each type of input character. Our algorithm computes directional features for alphanumeric input mapped on to a hexagonal lattice. The algorithm implements size and scale invariance that is a requirement for achieving a reasonably good recognition rate. Functional performance has been verified for an hexagonal lattice mapped input on the data obtained from the US postal service handwritten character database. In this thesis, we implemented the algorithm in a Xilinx FPGA (XC4xxx series).
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Date Issued
1994
PURL
http://purl.flvc.org/fcla/dt/15103
Subject Headings
Algorithms, Pattern recognition systems--Computer simulation, Optical character recognition devices--Computer simulation
Format
Document (PDF)
Handwritten digit recognition using neural network integrated chips
Title
Handwritten digit recognition using neural network integrated chips.
Creator
Bidari, Ravindra Chandrashekar., Florida Atlantic University, Shankar, Ravi
Abstract/Description
Development of a handwritten digit recognition system for real time applications is a feasible goal today due to the many advances pertinent to VLSI. In this research we address the issue of mapping our neural net classification algorithm to Intel's commercially available general purpose Neural Network Chip, 80170NX (ETANN). Most of the proposed techniques used for character recognition have been validated by our research group using various software and hardware simulation methods. The...
Show moreDevelopment of a handwritten digit recognition system for real time applications is a feasible goal today due to the many advances pertinent to VLSI. In this research we address the issue of mapping our neural net classification algorithm to Intel's commercially available general purpose Neural Network Chip, 80170NX (ETANN). Most of the proposed techniques used for character recognition have been validated by our research group using various software and hardware simulation methods. The objective of this thesis was to develop a practical hardware system to perform the final step of classification of handwritten digits in an Optical Character Recognition (OCR) system. Such a hardware implementation would increase the classification speed and also would permit testing in a real life application environment. An efficient mapping scheme was evolved to map the modules of a limited interconnect classification algorithm, CLUMP, to a minimum number of ETANN chips. The hardware modules to interface the ETANN chips to MC68000 education board have been developed and tested. The proposed system is estimated to process the features input in 336 $\mu$s, for our specific implementation, with 12 clock phases and 3 ETANN chips.
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Date Issued
1992
PURL
http://purl.flvc.org/fcla/dt/14838
Subject Headings
Optical character recognition devices--Computer simulation, Pattern recognition systems--Computer simulation
Format
Document (PDF)
VLSI implementable thinning algorithm
Title
A VLSI implementable thinning algorithm.
Creator
Zhang, Wei, Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description
Thinning is a very important step in a Character Recognition System. This thesis evolves a thinning algorithm that can be hardware implemented to improve the speed of the process. The software thinning algorithm features a simple set of rules that can be applied on both hexagonal and orthogonal character images. The hardware architecture features the SIMD structure, simple processing elements and near neighbor communications. The algorithm was simulated against the U.S. Postal Service...
Show moreThinning is a very important step in a Character Recognition System. This thesis evolves a thinning algorithm that can be hardware implemented to improve the speed of the process. The software thinning algorithm features a simple set of rules that can be applied on both hexagonal and orthogonal character images. The hardware architecture features the SIMD structure, simple processing elements and near neighbor communications. The algorithm was simulated against the U.S. Postal Service Character Database. The architecture, evolved with consideration of both the software constraints and the physical layout limitations, was simulated using VHDL hardware description language. Subsequent to VLSI design and simulations the chip was fabricated. The project provides for a feasibility study in utilizing the parallel processor architecture for the implementation of a parallel image thinning algorithm. It is hoped that such a hardware implementation will speed up the processing and lead eventually to a real time system.
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Date Issued
1992
PURL
http://purl.flvc.org/fcla/dt/14837
Subject Headings
Optical character recognition devices--Computer simulation, Algorithms, Integrated circuits--Very large scale integration
Format
Document (PDF)