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Title: ANALYSIS AND COMPARISON OF THE RELEASE WHEN DONE AND RELEASE ON REQUEST BUS ARBITRATION METHODS (MAKOV CHAIN, MULTIPROCESSOR, BUS MASTER).
Creator: SINIBALDI, JOHN CLAUDE., Florida Atlantic University, Marcovitz, Alan B., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: A comparative analysis of two methods of bus arbitration used by a multiprocessing system with a single main bus is performed. The major performance parameters are delay time and the average number of active processors, called processing power. The bus arbitration methods are described using state and timing diagrams. Multiprocessor systems using these methods of arbitration are then modeled using Markov chains to enable the formulation of processing power. From processing power other...
Show moreA comparative analysis of two methods of bus arbitration used by a multiprocessing system with a single main bus is performed. The major performance parameters are delay time and the average number of active processors, called processing power. The bus arbitration methods are described using state and timing diagrams. Multiprocessor systems using these methods of arbitration are then modeled using Markov chains to enable the formulation of processing power. From processing power other performance parameters can be derived. A comparison is then made among the two bus arbitration methods based on the analytical results where processors access the bus at an equal rate. Simulations of multiprocessor systems using either of the two arbitration methods were performed to validate the analytical models for equal bus request rates. Simulations are also performed of a system of processors using the main bus at unequal rates.
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Date Issued: 1986
PURL: http://purl.flvc.org/fcla/dt/14350
Subject Headings: Multiprocessors, System design
Format: Document (PDF)

Title: OPTIMAL SCHEDULING OF PROCESSES FOR A NETWORK OF TRANSPUTERS (MULTIPROCESSOR, OCCAM, CONCURRENT PROCESSING).
Creator: NGO, TON ANH., Florida Atlantic University, Fernandez, Eduardo B., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Concurrency at both the hardware and software level has recently been considered as the solution to the classic Von Neuman bottleneck in system design. Introduced by Inmos, the Occam language and the Transputer microprocessor provide simple and elegant building blocks for a concurrent system. This thesis proposes a set of algorithms to find an optimal deterministic schedule for an Occam program executed on a network of Transputers. Also discussed are features of the network relevant to the...
Show moreConcurrency at both the hardware and software level has recently been considered as the solution to the classic Von Neuman bottleneck in system design. Introduced by Inmos, the Occam language and the Transputer microprocessor provide simple and elegant building blocks for a concurrent system. This thesis proposes a set of algorithms to find an optimal deterministic schedule for an Occam program executed on a network of Transputers. Also discussed are features of the network relevant to the problem of scheduling, and a complete example is provided to illustrate the scheduler. The approaches described can be used as a basis for implementing a flexible general purpose multiprocessor system.
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Date Issued: 1986
PURL: http://purl.flvc.org/fcla/dt/14351
Subject Headings: Multiprocessors, Computer networks
Format: Document (PDF)

Title: Memory latency evaluation in cluster-based cache-coherent multiprocessor systems with different interconnection topologies.
Creator: Asaduzzaman, Abu Sadath Mohammad, Florida Atlantic University, Mahgoub, Imad
Abstract/Description: This research investigates memory latency of cluster-based cache-coherent multiprocessor systems with different interconnection topologies. We focus on a cluster-based architecture which is a variation of Stanford DASH architecture. The architecture, also, has some similarities with the STiNG architecture from Sequent Computer System Inc. In this architecture, a small number of processors and a portion of shared-memory are connected through a bus inside each cluster. As the number of...
Show moreThis research investigates memory latency of cluster-based cache-coherent multiprocessor systems with different interconnection topologies. We focus on a cluster-based architecture which is a variation of Stanford DASH architecture. The architecture, also, has some similarities with the STiNG architecture from Sequent Computer System Inc. In this architecture, a small number of processors and a portion of shared-memory are connected through a bus inside each cluster. As the number of processors per cluster is small, snoopy protocol is used inside each cluster. Each processor has two levels of caches and for each cluster a separate directory is maintained. Clusters are connected using directory-based scheme through an interconnection network to make the system scaleable. Trace-driven simulation has been developed to evaluate the overall memory latency of this architecture using three different network topologies, namely ring, mesh, and hypercube. For each network topology, the overall memory latency has been evaluated running a representative set of SPLASH-2 applications. Simulation results show that, the cluster-based multiprocessor system with hypercube topology outperforms those with mesh and ring topologies.
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Date Issued: 1997
PURL: http://purl.flvc.org/fcla/dt/15447
Subject Headings: Computer network architectures, Multiprocessors
Format: Document (PDF)

Title: A multiprocessor simulator to test fault detection and reconfiguration algorithms.
Creator: Bhathija, Unmesh Jethanand., Florida Atlantic University, Fernandez, Eduardo B.
Abstract/Description: In recent years multiprocessor systems are becoming increasingly important in critical applications. In particular, their fault tolerance properties are of great importance for their ability to be used in these type of applications. We have developed a multiprocessor simulator that can be used to test different fault detection algorithms. The processors must have four communication links. This simulator operates by passing messages between processors. An algorithm was developed for routing...
Show moreIn recent years multiprocessor systems are becoming increasingly important in critical applications. In particular, their fault tolerance properties are of great importance for their ability to be used in these type of applications. We have developed a multiprocessor simulator that can be used to test different fault detection algorithms. The processors must have four communication links. This simulator operates by passing messages between processors. An algorithm was developed for routing the messages among the processors. The simulator can also be used to try different reconfiguration strategies. In particular we have tested Malek's comparison algorithm using different multiprocessor configurations. We also developed a program which determines the configuration of an unknown network of transputers.
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Date Issued: 1990
PURL: http://purl.flvc.org/fcla/dt/14622
Subject Headings: Multiprocessors, Fault-tolerant computing
Format: Document (PDF)

Title: A memory-efficient directory-based cache coherence scheme for large-scale multiprocessors.
Creator: Heragu, Sampath C., Florida Atlantic University, Mahgoub, Imad
Abstract/Description: Caches are used in shared memory multiprocessors to reduce the effective memory latency, and network and memory bandwidth requirements. But the data spreading across the caches leads to the cache coherence problem. In this thesis, a new directory based cache coherence scheme, called the cache-vector protocol, is proposed and evaluated. The said scheme entails a low memory overhead but delivers a performance that is very close to that of the scheme proposed by Censier and Feautrier (3), which...
Show moreCaches are used in shared memory multiprocessors to reduce the effective memory latency, and network and memory bandwidth requirements. But the data spreading across the caches leads to the cache coherence problem. In this thesis, a new directory based cache coherence scheme, called the cache-vector protocol, is proposed and evaluated. The said scheme entails a low memory overhead but delivers a performance that is very close to that of the scheme proposed by Censier and Feautrier (3), which offers the best performance of all the directory based schemes. The performance of the cache-vector protocol is evaluated using trace-driven simulation. A figure of merit which takes into account the average memory latency, network traffic and the hardware overhead is introduced and used as the basis of comparison between the two schemes. The simulation results indicate that the cache-vector protocol is a viable solution to the cache coherence problem in large scale multiprocessors.
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Date Issued: 1995
PURL: http://purl.flvc.org/fcla/dt/15163
Subject Headings: Cache memory, Multiprocessors, Memory hierarchy (Computer science)
Format: Document (PDF)

Title: A recovery metaprogram for fault diagnosis in a network of processors.
Creator: Pendse, Sateesh V., Florida Atlantic University, Fernandez, Eduardo B., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Recent advances in computer technology have increased the performance of computers, but application requirements will always exceed the performance level available today. This requires the use of multiprocessors. The importance of multiprocessor systems is increasing due to many reasons, one of which is reliability. Reliability is also an important aspect in any computer system design. For reliable operation the system should be able to detect and locate most of its faults. The idea of using...
Show moreRecent advances in computer technology have increased the performance of computers, but application requirements will always exceed the performance level available today. This requires the use of multiprocessors. The importance of multiprocessor systems is increasing due to many reasons, one of which is reliability. Reliability is also an important aspect in any computer system design. For reliable operation the system should be able to detect and locate most of its faults. The idea of using a set of processes collectively known as a Recovery Metaprogram (RMP) is applied in this thesis to system diagnosis. Several error location algorithms are analyzed and compared. Most of them are comparison methods. A new algorithm, called Duplication algorithm, is developed and analyzed. Primitives, oriented to the specific functions of error diagnosis, required by the RMP to coordinate recovery functions are also developed in this thesis.
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Date Issued: 1990
PURL: http://purl.flvc.org/fcla/dt/14656
Subject Headings: Fault location (Engineering)--Data processing, Multiprocessors
Format: Document (PDF)

Title: SHINE: An integrated environment for software hardware co-design.
Creator: Jayadevappa, Suryaprasad., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: The rapid evolution of silicon technology has brought exponential benefits in cost, scale of integration, power per function, size per function and speed. The ability to place multiple function "systems" on a single silicon chip, reduce development cycle while increasing product functionality, performance and quality. With this increased complexity, ability to model at high level of abstraction becomes crucial. Also, the fact that no known existing complete system on chip design packages with...
Show moreThe rapid evolution of silicon technology has brought exponential benefits in cost, scale of integration, power per function, size per function and speed. The ability to place multiple function "systems" on a single silicon chip, reduce development cycle while increasing product functionality, performance and quality. With this increased complexity, ability to model at high level of abstraction becomes crucial. Also, the fact that no known existing complete system on chip design packages with perfect tools, models, and formalisms further slows down and complicates the development. This dissertation provides an integrated environment for hardware software co-design at a high level of abstraction. We have developed a SystemC based cockpit for this purpose. The cockpit, known as SHINE consists of many components including architectural components, operating system components, and application software components. The ability to represent and manipulate these components at high levels of abstraction is a major challenge. To address these challenges we have developed a set of principles. Important principles evolved are synergy of separation of concerns, reusability, flexibility, ease of use, and support for multiple levels of abstraction. 'Synergy of Separation of Concerns' helps in maintaining transparency during all instances in the development of the integrated environment. One application is transparent to another application and in turn to the system architecture. Also in the system architecture, each module is designed independent of other modules. Well defined interfaces enable this transparency and easier to integrate. This also enhances component reuse and overall design environment modularity. 'Ease of Use' allows the user to shorten the learning curve involved. In SHINE, 'Flexibility' is addressed via support for plug-and-play of components in the design environment. We provide results to show the implementation of these principles. SHINE provides a cost-effective mechanism to develop a system co-design infrastructure. This will lead to early system verification and performance estimation resulting in shorter time-to-market. The design flow developed is structured and is easily extended. This is an exploratory study that is the result of a long term industrial collaboration to enhance design productivity. Significantly more work lies ahead in developing an industry standard tool and methodology.
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Date Issued: 2003
PURL: http://purl.flvc.org/fau/fd/FADT12065
Subject Headings: Computer architecture, System design, Systems software, Multiprocessors
Format: Document (PDF)

Title: Fault tolerant scheduling for multiprocessor systems.
Creator: Mahanthi, Gangadhar., Florida Atlantic University, Wu, Jie, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: In the last few years, it has become profound to achieve higher performance of computers by solely upgrading logic technology. This required a move to a parallel processing system or a multiprocessor system in order to build faster computer systems. The importance of multiprocessor systems is increasing due to many reasons, one of which is reliability. In a multiprocessor system, a number of tasks may concurrently exist. To operate the system efficiently, one must carefully schedule the tasks...
Show moreIn the last few years, it has become profound to achieve higher performance of computers by solely upgrading logic technology. This required a move to a parallel processing system or a multiprocessor system in order to build faster computer systems. The importance of multiprocessor systems is increasing due to many reasons, one of which is reliability. In a multiprocessor system, a number of tasks may concurrently exist. To operate the system efficiently, one must carefully schedule the tasks. This thesis proposes a set of algorithms to schedule these tasks exploiting the inherent redundancy of processors in a multiprocessor system. Also discussed are some reliability issues and application to different networks with some examples.
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Date Issued: 1992
PURL: http://purl.flvc.org/fcla/dt/14822
Subject Headings: Multiprocessors, Fault-tolerant computing, Electronic digital computers--Reliability
Format: Document (PDF)

Title: The design and implementation of a simple master/slave interprocess-communication module.
Creator: Mandadi, Sanjay Reddy, Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: We explored the portability of various OS concepts to silicon. We wish to develop intellectual property blocks of various OS concepts, so that an embedded system designer has the option to mix and match. As a first step we have looked at inter-process communication (IPC) and Process Scheduling. We have implemented simple hardware building blocks for these. In our problem we utilize two processors, one each assigned as Master and Slave. Master is in control and implements the OS algorithms,...
Show moreWe explored the portability of various OS concepts to silicon. We wish to develop intellectual property blocks of various OS concepts, so that an embedded system designer has the option to mix and match. As a first step we have looked at inter-process communication (IPC) and Process Scheduling. We have implemented simple hardware building blocks for these. In our problem we utilize two processors, one each assigned as Master and Slave. Master is in control and implements the OS algorithms, while the Slave executes the user/application code. We show that these OS building blocks can be implemented in the hardware. Future effort of our group is to build a portfolio of OS IP blocks and explore optimization for various applications.
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Date Issued: 2000
PURL: http://purl.flvc.org/fcla/dt/12690
Subject Headings: Operating systems (Computers), Computer networks--Design and construction, Multiprocessors
Format: Document (PDF)

Title: Load balancing on multiprocessor systems.
Creator: More, Hemant B., Florida Atlantic University, Wu, Jie, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: The utilization of a multiprocessor system is enhanced when idle time of processors is reduced. Allocation of processes from overloaded processors to idle processors can balance the load on multiprocessor systems and increase system throughput by reducing the process execution time. This thesis presents a study of parameters, issues and existing algorithms related to load balancing. The performance of load balancing on hypercubes using three new algorithms is explored and analyzed. A new...
Show moreThe utilization of a multiprocessor system is enhanced when idle time of processors is reduced. Allocation of processes from overloaded processors to idle processors can balance the load on multiprocessor systems and increase system throughput by reducing the process execution time. This thesis presents a study of parameters, issues and existing algorithms related to load balancing. The performance of load balancing on hypercubes using three new algorithms is explored and analyzed. A new algorithm to balance load on hypercubes in the presence of link faults is presented and analyzed here. Another algorithm to balance load on hypercube systems containing faulty processors is proposed and studied. The applicability of load balancing to real life problems is demonstrated by showing that the execution of branch and bound problem on hypercubes speeds up when load balancing is used.
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Date Issued: 1993
PURL: http://purl.flvc.org/fcla/dt/14957
Subject Headings: Hypercube networks (Computer networks), Multiprocessors, Fault-tolerant computing
Format: Document (PDF)

Title: Correctness analysis of cache conherence protocols using Petri nets.
Creator: Hassan, Ahmed Kamal., Florida Atlantic University, Mahgoub, Imad
Abstract/Description: The use of cache memories in multiprocessor systems increases the overall systems performance. Caches reduce the amount of network traffic and provide a solution to the memory contention problem. However, caches introduce memory consistency problems. The existence of multiple cache copies of a memory block will result in an inconsistent view of memory if one processor changes a value in its associated cache. Cache coherence protocols are algorithms designed in software or hardware to maintain...
Show moreThe use of cache memories in multiprocessor systems increases the overall systems performance. Caches reduce the amount of network traffic and provide a solution to the memory contention problem. However, caches introduce memory consistency problems. The existence of multiple cache copies of a memory block will result in an inconsistent view of memory if one processor changes a value in its associated cache. Cache coherence protocols are algorithms designed in software or hardware to maintain memory consistency. With the increased complexity of some of the more recent protocols, testing for the correctness of these protocols becomes an issue that requires more elaborate work. In this thesis, correctness analysis of a selected group of representative cache coherence protocols was performed using Petri nets as a modeling and analysis tool. First, the Petri net graphs for these protocols were designed. These graphs were built by following the logical and coherence actions performed by the protocols in response to the different processors' requests that threatens memory consistency. Correctness analysis was then performed on these graphs.
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Date Issued: 1997
PURL: http://purl.flvc.org/fcla/dt/15366
Subject Headings: Cache memory, Multiprocessors, Computer network protocols, Petri nets
Format: Document (PDF)

Title: A heterogeneous multiprocessor architecture for workstations.
Creator: Bealkowski, Richard., Florida Atlantic University, Fernandez, Eduardo B., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Providing multiprocessor capability to the class of computers commonly referred to as personal workstations is the next evolutionary step in their development. Uniprocessor workstations limit the user in throughput, reliability, functionality, and architecture. Multiprocessor workstations have the potential of increasing system throughput. A multiprocessor system with expanded architecture derived from a set of heterogeneous processors gives the user a diverse application base within a single...
Show moreProviding multiprocessor capability to the class of computers commonly referred to as personal workstations is the next evolutionary step in their development. Uniprocessor workstations limit the user in throughput, reliability, functionality, and architecture. Multiprocessor workstations have the potential of increasing system throughput. A multiprocessor system with expanded architecture derived from a set of heterogeneous processors gives the user a diverse application base within a single system. The replication and diversity offered in systems of this design, when coupled with fault-tolerant design techniques, enhances system reliability. A heterogeneous multiprocessor architecture is presented which combines loosely- and tightly-coupled configurations (multicomputer and multiprocessor). This architecture provides for incremental growth of the system, either by static or dynamic reconfiguration. The software view of the system is that of an object-oriented environment. The object-oriented approach is used to unify the heterogeneous nature of the system. The process is the unit of concurrency in the system and cooperating concurrent processes are supported. A set of system primitives are provided to support the requirements of a heterogeneous multiprocessing environment. A virtual machine layer controls the distribution of processes and allocation of resources in the system. A virtual network is used to provide communication paths and resource sharing. The virtual network is designed to be bridged to an external physical network. The system requirements for a secure and reliable operating environment are incorporated into the design. This system utilizes "hardware porting" as a means to overcome the lag of software support for hardware advances. Rather than software port an entire application base to a new system architecture, hardware porting brings the required instruction set architecture to the applications. This heterogeneous multiprocessor architecture builds on a popular system architecture, the scIBM PS/2 with the Micro Channel system bus. Incorporating a second bus, the scSCSI bus, as a system extension is explored.
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Date Issued: 1989
PURL: http://purl.flvc.org/fcla/dt/12242
Subject Headings: Microcomputer workstations, Multiprocessors, Object-oriented programming (Computer science), Computer architecture
Format: Document (PDF)

Title: Simulation analysis of cluster-based multiprocessor systems.
Creator: De Armas, Mario Ernesto., Florida Atlantic University, Mahgoub, Imad
Abstract/Description: Multiprocessor systems have demonstrated great potential for meeting the ever increasing demand for higher performance. In this thesis, we develop simulation models with fewer and more realistic assumptions to evaluate the performance of the circuit-switched cluster-based multiprocessor system. We then introduce a packet-switched variation of the cluster-based architecture and develop simulation models to evaluate its performance. The analysis of the cluster-based systems is performed for...
Show moreMultiprocessor systems have demonstrated great potential for meeting the ever increasing demand for higher performance. In this thesis, we develop simulation models with fewer and more realistic assumptions to evaluate the performance of the circuit-switched cluster-based multiprocessor system. We then introduce a packet-switched variation of the cluster-based architecture and develop simulation models to evaluate its performance. The analysis of the cluster-based systems is performed for both uniform and non-uniform memory reference models. We conducted similar analysis for the crossbar and multiple-bus systems. Finally, the results of the cluster-based systems are compared to those obtained for the crossbar and the multiple-bus systems.
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Date Issued: 1993
PURL: http://purl.flvc.org/fcla/dt/14969
Subject Headings: Multiprocessors, Cluster analysis, Packet switching (Data transmission), Computer architecture, Computer simulation
Format: Document (PDF)

Title: Enhanced Fibonacci Cubes.
Creator: Qian, Haifeng., Florida Atlantic University, Wu, Jie, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: We propose the enhanced Fibonacci cube (EFC), which is defined based on the sequence Fn = 2(n-2) + 2F(n-4). We study its topological properties, embeddings, applications, routings, VLSI/WSI implementations, and its extensions. Our results show that EFC retains many properties of the hypercube. It contains the Fibonacci cube (FC) and extended Fibonacci cube of the same order as subgraphs and maintains virtually all the desirable properties of FC. EFC is even better in some structural...
Show moreWe propose the enhanced Fibonacci cube (EFC), which is defined based on the sequence Fn = 2(n-2) + 2F(n-4). We study its topological properties, embeddings, applications, routings, VLSI/WSI implementations, and its extensions. Our results show that EFC retains many properties of the hypercube. It contains the Fibonacci cube (FC) and extended Fibonacci cube of the same order as subgraphs and maintains virtually all the desirable properties of FC. EFC is even better in some structural properties, embeddings, applications and VLSI designs than FC or hypercube. With EFC, there are more cubes with various structures and sizes for selection, and more backup cubes into which faulty hypercubes can be reconfigured, which alleviates the size limitation of the hypercube and results in a higher level of fault tolerance.
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Date Issued: 1995
PURL: http://purl.flvc.org/fcla/dt/15196
Subject Headings: Integrated circuits--Very large scale integration, Hypercube networks (Computer networks), Algorithms, Fault-tolerant computing, Multiprocessors
Format: Document (PDF)

Title: Embedding binomial trees in faulty hypercube multiprocessors.
Creator: Luo, Yinqiu., Florida Atlantic University, Wu, Jie, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: We study the embedding of binomial trees with variable roots in faulty hypercubes. Based on novel embedding strategies, we propose three embedding algorithms with variable nodes as the root. The first algorithm can tolerate up to n - 1 faulty links, but the execution can be done within log2(n - 1) subcube splits. The second one can tolerate up to [(3(n - 1))\2] faulty links. The last one can tolerate up to [(3(n - 4))\2] faulty nodes.
Date Issued: 1996
PURL: http://purl.flvc.org/fcla/dt/15345
Subject Headings: Hypercube networks (Computer networks), Trees (Graph theory), Multiprocessors, Parallel processing (Electronic computers), Computer algorithms, Fault-tolerant computing, Embedded computer systems
Format: Document (PDF)

Multiprocessors (15)	+ -
Fault-tolerant computing (5)	+ -
Computer architecture (3)	+ -
Hypercube networks (Computer networks) (3)	+ -
Cache memory (2)	+ -

System design (2)	+ -
Algorithms (1)	+ -
Cluster analysis (1)	+ -
Computer algorithms (1)	+ -
Computer network architectures (1)	+ -
Computer network protocols (1)	+ -
Computer networks (1)	+ -
Computer networks--Design and construction (1)	+ -
Computer simulation (1)	+ -
Electronic digital computers--Reliability (1)	+ -
Embedded computer systems (1)	+ -
Fault location (Engineering)--Data processing (1)	+ -
Integrated circuits--Very large scale integration (1)	+ -
Memory hierarchy (Computer science) (1)	+ -
Microcomputer workstations (1)	+ -
Object-oriented programming (Computer science) (1)	+ -
Operating systems (Computers) (1)	+ -
Packet switching (Data transmission) (1)	+ -
Parallel processing (Electronic computers) (1)	+ -
Petri nets (1)	+ -
Systems software (1)	+ -
Trees (Graph theory) (1)	+ -

Florida Atlantic University (15)	+ -
College of Engineering and Computer Science (10)	+ -
Department of Computer and Electrical Engineering and Computer Science (10)	+ -
Fernandez, Eduardo B. (4)	+ -
Mahgoub, Imad (4)	+ -

Wu, Jie (4)	+ -
Shankar, Ravi (2)	+ -
Asaduzzaman, Abu Sadath Mohammad (1)	+ -
Bealkowski, Richard. (1)	+ -
Bhathija, Unmesh Jethanand. (1)	+ -
De Armas, Mario Ernesto. (1)	+ -
Hassan, Ahmed Kamal. (1)	+ -
Heragu, Sampath C. (1)	+ -
Jayadevappa, Suryaprasad. (1)	+ -
Luo, Yinqiu. (1)	+ -
Mahanthi, Gangadhar. (1)	+ -
Mandadi, Sanjay Reddy (1)	+ -
Marcovitz, Alan B. (1)	+ -
More, Hemant B. (1)	+ -
NGO, TON ANH. (1)	+ -
Pendse, Sateesh V. (1)	+ -
Qian, Haifeng. (1)	+ -
SINIBALDI, JOHN CLAUDE. (1)	+ -

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