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Novel multiplexer-based architectures for full adder design
Title
Novel multiplexer-based architectures for full adder design.
Creator
Al-Sheraidah, Abdulkarim K., Florida Atlantic University, Wang, Yuke
Abstract/Description
We propose five new Multiplexer-Based architectures for 1-bit full adder design. Using a 2-transistors multiplexer gate to implement the first architecture, we are able to produce a 12-transistor full adder cell, Comparing it to four different 10-transistors low-power full adder cells reported previously in literature, the new adder cell named MBA1-12T out performs all of them in power consumption and speed. By implementing those architectures using the 2-input CMOS multiplexer with pass...
Show moreWe propose five new Multiplexer-Based architectures for 1-bit full adder design. Using a 2-transistors multiplexer gate to implement the first architecture, we are able to produce a 12-transistor full adder cell, Comparing it to four different 10-transistors low-power full adder cells reported previously in literature, the new adder cell named MBA1-12T out performs all of them in power consumption and speed. By implementing those architectures using the 2-input CMOS multiplexer with pass-gates, five new high-performance full adder cells are obtained. Those new adder cells are tested along with the conventional 28-transistor CMOS adder cell. Testing results shows that the new adder cells have higher speed and lower power delay product values than the conventional 28-transistor CMOS adder cell.
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Date Issued
2000
PURL
http://purl.flvc.org/fcla/dt/12667
Subject Headings
Metal oxide semiconductors, Complementary, Digital integrated circuits
Format
Document (PDF)
An empirical methodology for foundry specific submicroncmos analog circuit design
Title
An empirical methodology for foundry specific submicroncmos analog circuit design.
Creator
Rivas-Torres, Wilfredo, Roth, Zvi S., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description
Analog CMOS amplifiers are the building blocks for many analog circuit applications such as Operational Amplifiers, Comparators, Analog to Digital converters and others. This dissertation presents empirical design methodologies that are both intuitive and easy to follow on how to design these basic building blocks. The design method involves two main phases. In the first phase NMOS and PMOS transistor design kits, provided by a semiconductor foundry, are fully characterized using a set of...
Show moreAnalog CMOS amplifiers are the building blocks for many analog circuit applications such as Operational Amplifiers, Comparators, Analog to Digital converters and others. This dissertation presents empirical design methodologies that are both intuitive and easy to follow on how to design these basic building blocks. The design method involves two main phases. In the first phase NMOS and PMOS transistor design kits, provided by a semiconductor foundry, are fully characterized using a set of simulation experiments. In the second phase the user is capable of modifying all the relevant circuit design parameters while directly observing the tradeoffs in the circuit performance specifications. The final design is a circuit that very closely meets a set of desired design specifications for the design parameters selected. That second phase of the proposed design methodology utilizes a graphical user interface in which the designer moves a series of sliders allowing assessment of various design tradeoffs. The theoretical basis for this design methodology involves the transconductance efficiency and inversion coefficient parameters. In this dissertation there are no restrictive assumptions about the MOS transistor models. The design methodology can be used with any submicron model supported by the foundry process and in this sense the methods included within are general and non-dependent on any specific MOSFET model (e.g. EKV or BSIM3). As part of the design tradeoffs assessment process variations are included during the design process rather than as part of some post-nominal-design analysis. One of the central design parameters of each transistor in the circuit is the MOSFET inversion coefficient. The calculation of the inversion coefficient necessitates the determination of an important process parameter known as the Technology Current. In this dissertation a new method to determine the technology current is developed. Y Parameters are used to characterize the CMOS process and this also helps in improving the technology current determination method. A study of the properties of the technology current proves that indeed a single long channel saturated MOS transistor can be used to determine a fixed technology current value that is used in subsequent submicron CMOS design. Process corners and the variability of the technology current are also studied and the universality of the transconductance efficiency versus inversion coefficient response is shown to be true even in the presence of process variability.
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Date Issued
2013
PURL
http://purl.flvc.org/fau/fd/FA0004050
Subject Headings
Electron transport, Integrated circuits -- Design and construction, Metal oxide semiconductors, Complementary -- Mathematical models
Format
Document (PDF)
Design of 10-transistor low-power full adders
Title
Design of 10-transistor low-power full adders.
Creator
Bui, Hung Tien., Florida Atlantic University, Wang, Yuke
Abstract/Description
We propose two approaches to design 1-bit full adders which can yield good performance at low power consumption. In the first approach, we design XOR/XNOR gates using a minimal number of CMOS transistors. Comparing with 10 different XOR/XNOR gates reported in literature, the new XOR/XNOR gates consume less power. The gates consisting of the smallest number of transistors are combined to create 1-bit full adders. The process is systematic and yields a total of 42 10-transistor full adders, 41...
Show moreWe propose two approaches to design 1-bit full adders which can yield good performance at low power consumption. In the first approach, we design XOR/XNOR gates using a minimal number of CMOS transistors. Comparing with 10 different XOR/XNOR gates reported in literature, the new XOR/XNOR gates consume less power. The gates consisting of the smallest number of transistors are combined to create 1-bit full adders. The process is systematic and yields a total of 42 10-transistor full adders, 41 of which are new. Simulation results show that most of the new adders perform better than a previously existing 10-transistor adder and a complementary CMOS adder in terms of power and speed with heavier load. Three adders consistently perform better. In the second approach, we utilized a method called the centralized design to create four new 10-transistor full adders. Simulation results show that these new adders perform better than the previously existing 10-transistor and the complementary CMOS adder.
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Date Issued
2000
PURL
http://purl.flvc.org/fcla/dt/15759
Subject Headings
Digital integrated circuits, Low voltage integrated circuits, Metal oxide semiconductors, Complementary
Format
Document (PDF)
Low-power design of an ALU
Title
Low-power design of an ALU.
Creator
Agarwal, Ankur, Florida Atlantic University, Pandya, Abhijit S.
Abstract/Description
There is a mushrooming demand for battery operated applications that require intensive computation in portable environments. This has motivated the research and development of techniques that reduce power in CMOS digital circuits while maintaining their computational throughput. The two essentials to achieve a low power design are miniaturization and long battery life. Lowering the supply voltage is one of the most effective ways to achieve low-power performance as power dissipation in...
Show moreThere is a mushrooming demand for battery operated applications that require intensive computation in portable environments. This has motivated the research and development of techniques that reduce power in CMOS digital circuits while maintaining their computational throughput. The two essentials to achieve a low power design are miniaturization and long battery life. Lowering the supply voltage is one of the most effective ways to achieve low-power performance as power dissipation in digital CMOS circuits is approximately proportional to the square of supply voltage. The basic idea behind this thesis is that it proposes new designs of transfer gate based logical circuits, which use lower supply voltage and less number of transistors than the conventional designs. This work evaluates the obtained results from the proposed designs of the low-power ALU with that from the standard CMOS, other low power designs namely, Wang's XOR, XNOR and Inverter based gates. It was observed that the proposed designs perform better in terms of power consumption than the standard CMOS designs, and the other low power designs mentioned above.
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Date Issued
2003
PURL
http://purl.flvc.org/fcla/dt/13017
Subject Headings
Metal oxide semiconductors, Complementary, Low voltage integrated circuits, Verilog (Computer hardware description language), Logic design
Format
Document (PDF)
CMOS VLSI Design of a Bluetooth™ Receiver Front-End: Performance Evaluation via ADS™-Based Simulations
Title
CMOS VLSI Design of a Bluetooth™ Receiver Front-End: Performance Evaluation via ADS™-Based Simulations.
Creator
Talbot, Bethany J., Neelakanta, Perambur S., Florida Atlantic University, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description
The research addressed and deliberated in this thesis refers to CMOS VLSI design approach of a Bluetooth™ receiver front-end. The performance outcome o f the design is verified with ADS™ RF simulation tool. Essentially the thesis offers an outline on the Bluetooth™ technology and its RF front-end component requirements. The relevant specifications of the designed front-end blocks are identified and are in concurrence with CMOS technology based topologies. For each block identified, both...
Show moreThe research addressed and deliberated in this thesis refers to CMOS VLSI design approach of a Bluetooth™ receiver front-end. The performance outcome o f the design is verified with ADS™ RF simulation tool. Essentially the thesis offers an outline on the Bluetooth™ technology and its RF front-end component requirements. The relevant specifications of the designed front-end blocks are identified and are in concurrence with CMOS technology based topologies. For each block identified, both circuit parameters and device characteristics are chosen as per available design formulations and empirical results in open literature. Specifically, the topology sections designed include antenna input matching, transmit/receive switch, necessary filters, low noise amplifier, mixer and phase lock loop units. The numerical TM, (designed) circuit parameters are duly addressed in appropriate ADS simulation tools and performance evaluations are conducted. Observed results including any deviations are identified and reported. The thesis concludes with a summary and indicates direction for future work.
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Date Issued
2007
PURL
http://purl.flvc.org/fau/fd/FA00012559
Subject Headings
Integrated circuits--Very large scale integration--Design and construction, Metal oxide semiconductors, Complementary, Bluetooth technology, Network performance (Telecommunication)
Format
Document (PDF)
DCVS logic synthesis
Title
DCVS logic synthesis.
Creator
Xiao, Kang., Florida Atlantic University, Barrett, Raymond L. Jr., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description
Implementation of CMOS combinational logic with Differential Cascode Voltage Switch logic (DCVS) may have many advantages over the traditional CMOS logic approaches with respect to device count, layout density and timing. DCVS is an ideal target technology for a logic synthesis system in that it provides a complete function cover by providing the function and its complement simultaneously. DCVS is also more testable due to this. We have developed for IBM's DCVS technology a synthesis...
Show moreImplementation of CMOS combinational logic with Differential Cascode Voltage Switch logic (DCVS) may have many advantages over the traditional CMOS logic approaches with respect to device count, layout density and timing. DCVS is an ideal target technology for a logic synthesis system in that it provides a complete function cover by providing the function and its complement simultaneously. DCVS is also more testable due to this. We have developed for IBM's DCVS technology a synthesis algorithm and a new test generation approach, that are based on topologies rather than individual logic functions. We have found that 19 and 363 DCVS topologies can represent 256 and 65,536 functions, respectively, for the 3- and 4-varaible cases. Physical defect analysis was conducted with the aid of a building block approach to analyze the n-type logic tree and provides a basis for evolving hierarchical test pattern generation for the topologies.
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Date Issued
1992
PURL
http://purl.flvc.org/fcla/dt/14850
Subject Headings
Integrated circuits--Very large scale integration--Data processing, Metal oxide semiconductors, Complementary, Computer-aided design, Electronic systems, Logic design--Data processing
Format
Document (PDF)
low power and high performance centralized full adder
Title
A low power and high performance centralized full adder.
Creator
Srivastav, Sidharth., Florida Atlantic University, Pandya, Abhijit S., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description
In this thesis, we proposed a low power and high performance architecture for 1-bit full adder design. The proposed architecture was proven to offer a wide range of performance ability in terms of power consumption and speed. We implemented the architecture using a 2-input 2 multiplexers, an XOR and an XNOR gate. The proposed architecture and the Standard full adder were designed and simulated using Lasi, Winspice and Silos. Silos, a logic simulation environment was used in the design and...
Show moreIn this thesis, we proposed a low power and high performance architecture for 1-bit full adder design. The proposed architecture was proven to offer a wide range of performance ability in terms of power consumption and speed. We implemented the architecture using a 2-input 2 multiplexers, an XOR and an XNOR gate. The proposed architecture and the Standard full adder were designed and simulated using Lasi, Winspice and Silos. Silos, a logic simulation environment was used in the design and verification of the proposed architecture and the standard full adder that were modeled with Verilog hardware description language. Lasi was used for the layout design of the proposed architecture and the standard full adder. After the layout, both the architectures were compiled separately using LASICKT and a corresponding .CIR file was generated. The .CIR file was imported and executed into WINSPICE3 for the simulation of the circuit.
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Date Issued
2004
PURL
http://purl.flvc.org/fcla/dt/13188
Subject Headings
Digital integrated circuits, Metal oxide semiconductors, Complementary, Integrated circuits--Design and contruction, Verilog (Computer hardware description language), Mixed signal circuits--Design and construction--Computer-aided design
Format
Document (PDF)