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CMOS VLSI Design of a Bluetooth™ Receiver Front-End: Performance Evaluation via ADS™-Based Simulations
Title
CMOS VLSI Design of a Bluetooth™ Receiver Front-End: Performance Evaluation via ADS™-Based Simulations.
Creator
Talbot, Bethany J., Neelakanta, Perambur S., Florida Atlantic University, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description
The research addressed and deliberated in this thesis refers to CMOS VLSI design approach of a Bluetooth™ receiver front-end. The performance outcome o f the design is verified with ADS™ RF simulation tool. Essentially the thesis offers an outline on the Bluetooth™ technology and its RF front-end component requirements. The relevant specifications of the designed front-end blocks are identified and are in concurrence with CMOS technology based topologies. For each block identified, both...
Show moreThe research addressed and deliberated in this thesis refers to CMOS VLSI design approach of a Bluetooth™ receiver front-end. The performance outcome o f the design is verified with ADS™ RF simulation tool. Essentially the thesis offers an outline on the Bluetooth™ technology and its RF front-end component requirements. The relevant specifications of the designed front-end blocks are identified and are in concurrence with CMOS technology based topologies. For each block identified, both circuit parameters and device characteristics are chosen as per available design formulations and empirical results in open literature. Specifically, the topology sections designed include antenna input matching, transmit/receive switch, necessary filters, low noise amplifier, mixer and phase lock loop units. The numerical TM, (designed) circuit parameters are duly addressed in appropriate ADS simulation tools and performance evaluations are conducted. Observed results including any deviations are identified and reported. The thesis concludes with a summary and indicates direction for future work.
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Date Issued
2007
PURL
http://purl.flvc.org/fau/fd/FA00012559
Subject Headings
Integrated circuits--Very large scale integration--Design and construction, Metal oxide semiconductors, Complementary, Bluetooth technology, Network performance (Telecommunication)
Format
Document (PDF)
VLSI implementable learning algorithm
Title
A VLSI implementable learning algorithm.
Creator
Ruiz, Laura V., Florida Atlantic University, Pandya, Abhijit S., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description
A top-down design methodology using hardware description languages (HDL's) and powerful design, analysis, synthesis and layout software tools for electronic circuit design is described and applied to the design of a single layer artificial neural network that incorporates on-chip learning. Using the perception learning algorithm, these simple neurons learn a classification problem in 10.55 microseconds in one application. The objective is to describe a methodology by following the design of a...
Show moreA top-down design methodology using hardware description languages (HDL's) and powerful design, analysis, synthesis and layout software tools for electronic circuit design is described and applied to the design of a single layer artificial neural network that incorporates on-chip learning. Using the perception learning algorithm, these simple neurons learn a classification problem in 10.55 microseconds in one application. The objective is to describe a methodology by following the design of a simple network. This methodology is later applied in the design of a novel architecture, a stochastic neural network. All issues related to algorithmic design for VLSI implementability are discussed and results of layout and timing analysis given over software simulations. A top-down design methodology is presented, including a brief introduction to HDL's and an overview of the software tools used throughout the design process. These tools make it possible now for a designer to complete a design in a relative short period of time. In-depth knowledge of computer architecture, VLSI fabrication, electronic circuits and integrated circuit design is not fundamental to accomplish a task that a few years ago would have required a large team of specialized experts in many fields. This may appeal to researchers from a wide background of knowledge, including computer scientists, mathematicians, and psychologists experimenting with learning algorithms. It is only in a hardware implementation of artificial neural network learning algorithms that the true parallel nature of these architectures could be fully tested. Most of the applications of neural networks are basically software simulations of the algorithms run on a single CPU executing sequential simulations of a parallel, richly interconnected architecture. This dissertation describes a methodology whereby a researcher experimenting with a known or new learning algorithm will be able to test it as it was intentionally designed for, on a parallel hardware architecture.
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Date Issued
1996
PURL
http://purl.flvc.org/fcla/dt/12453
Subject Headings
Integrated circuits--Very large scale integration--Design and construction, Neural networks (Computer science)--Design and construction, Computer algorithms, Machine learning
Format
Document (PDF)