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Title: PIREN(copyright): A heuristic algorithm for standard cell placement.
Creator: Horvath, Elizabeth Iren., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: The placement problem is an important part in the design process of VLSI chips. It is necessary to have a proper placement so that all connections between modules in a chip can be routed in a minimum area without violating any physical or electrical constraints. Current algorithms either do not give optimum solutions, are computationally slow, or are difficult to parallelize. PIREN(copyright) is a parallel implementation of a force directed algorithm which seeks to overcome the large amount...
Show moreThe placement problem is an important part in the design process of VLSI chips. It is necessary to have a proper placement so that all connections between modules in a chip can be routed in a minimum area without violating any physical or electrical constraints. Current algorithms either do not give optimum solutions, are computationally slow, or are difficult to parallelize. PIREN(copyright) is a parallel implementation of a force directed algorithm which seeks to overcome the large amount of computer time associated with solving the placement problem. Each active processor in the massively parallel SIMD machine, the MasPar MP-2.2, can perform in parallel the computation necessary to place cells in an optimum location relative to one another based upon the connectivity between cells. This is due to a salient feature of the serial algorithm which allows multiple permutations to be made simultaneously on all modules in order to minimize the objective function. The serial implementation of PIREN(copyright) compares favorably in both run time and layout quality to the simulated annealing based algorithm, TimberWolf3.2$\sp\copyright$. The parallel implementation on the MP-2.2 has a speedup of 4.5 to 58.0 over the serial version of PIREN$\sp\copyright$ running of the VAX 6320, while producing layouts for several MCNC benchmarks which are of the same quality as those produced by the serial implementation.
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Date Issued: 1992
PURL: http://purl.flvc.org/fcla/dt/12301
Subject Headings: Integrated circuits--Very large scale integration, Algorithms
Format: Document (PDF)

Title: SEMI-CUSTOM DESIGN OF A MICROPROGRAMMED TESTABLE REDUCED INSTRUCTION SET COMPUTER.
Creator: POENATEETAI, VIWAT., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: The concept of a Reduced Instruction Set Computer (RISC) has evolved out of a desire to enhance the performance of a computer. We present here a detailed design of a Testable Reduced Instruction Set Computer (TRISC) that utilizes a Multiple Register Set. Level Sensitive Scan Design (LSSD) is used to incorporate testability into our design. We first evolved a functional description of the design using Digital Design Language (DDL) a hardware programming language. We then entered the schematic...
Show moreThe concept of a Reduced Instruction Set Computer (RISC) has evolved out of a desire to enhance the performance of a computer. We present here a detailed design of a Testable Reduced Instruction Set Computer (TRISC) that utilizes a Multiple Register Set. Level Sensitive Scan Design (LSSD) is used to incorporate testability into our design. We first evolved a functional description of the design using Digital Design Language (DDL) a hardware programming language. We then entered the schematic of the design into Daisy's Logician V, a CAD/CAE workstation, using NCR CMOSII Digital Standard Cell Library. We then performed a unit delay simulation on the hierarchical design database to ascertain the logical functioning of the system.
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Date Issued: 1986
PURL: http://purl.flvc.org/fcla/dt/14284
Subject Headings: Computer architecture, Integrated circuits--Very large scale integration
Format: Document (PDF)

Title: Graph labeling and non-separating trees.
Creator: Gottipati, Chenchu B., Locke, Stephen C., Florida Atlantic University, Charles E. Schmidt College of Science, Department of Mathematical Sciences
Abstract/Description: This dissertation studies two independent problems, one is about graph labeling and the other problem is related to connectivity condition in a simple graph. Graph labeling is a rapidly developing area of research in graph theory, having connections with a variety of application-oriented areas such as VLSI optimization, data structures and data representation. Furthermore, the connectivity conditions in a simple graphs may help us to study the new aspects of ad hoc networks, social networks...
Show moreThis dissertation studies two independent problems, one is about graph labeling and the other problem is related to connectivity condition in a simple graph. Graph labeling is a rapidly developing area of research in graph theory, having connections with a variety of application-oriented areas such as VLSI optimization, data structures and data representation. Furthermore, the connectivity conditions in a simple graphs may help us to study the new aspects of ad hoc networks, social networks and web graphs. In chapter 2, we study path systems, reduced path systems and how to construct a super edge-graceful tree with any number of edges using path systems. First, we give an algorithm to reduce a labeled path system to a smaller labeled path system of a different type. First, we investigate the cases (m, k) = (3; 5) and (m, k) = (4; 7), where m is the number of paths and 2k is the length of each path, and then we give a generalization for any k, m = 3 and m = 4. We also describe a procedure to construct a super-edge-graceful tree with any number of edges.
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Date Issued: 2014
PURL: http://purl.flvc.org/fau/fd/FA00004289, http://purl.flvc.org/fau/fd/FA00004289
Subject Headings: Computational complexity, Computer graphics, Graph theory, Integrated circuits -- Very large scale integration, Mathematical optimization
Format: Document (PDF)

Title: Digital implementation issues of artificial neural networks.
Creator: Pesulima, Edward Elisha., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Recent years have seen the renaissance of the neural network field. Significant advances in our understanding of neural networks and its possible applications necessitate investigations into possible implementation strategies. Among the presently available implementation medium, digital VLSI hardware is one of the more promising because of its maturity and availability. We discuss various issues connected with implementing neural networks in digital VLSI hardware. A new sigmoidal transfer...
Show moreRecent years have seen the renaissance of the neural network field. Significant advances in our understanding of neural networks and its possible applications necessitate investigations into possible implementation strategies. Among the presently available implementation medium, digital VLSI hardware is one of the more promising because of its maturity and availability. We discuss various issues connected with implementing neural networks in digital VLSI hardware. A new sigmoidal transfer function is proposed with that implementation in mind. Possible realizations of the function for stochastic and deterministic neural networks are discussed. Simulation studies of applying neural networks in constraint optimization and learning problems are carried out. These simulations were performed strictly in integer arithmetic. Simulation results provides an encouraging outlook for implementing these neural network applications in digital VLSI hardware. Important results concerning the sizes of various network values were found for learning algorithms.
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Date Issued: 1990
PURL: http://purl.flvc.org/fcla/dt/14646
Subject Headings: Neural computers, Neural computers--Circuits, Integrated circuits--Very large scale integration
Format: Document (PDF)

Title: A VLSI implementation of a hexagonal topology CCD image sensor.
Creator: Madabushi, Vasudhevan., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: In this thesis we report a VLSI design implementation of an application specific, full-frame architecture CCD image sensor for a handwritten Optical Character Recognition system. The design is targeted to the MOSIS 2mu, 2-poly/ 2-metal n-buried channel CCD/CMOS technology. The front side illuminated CCD image sensor uses a transparent polysilicon gate structure and is comprised of 84 (H) x 100 (V) pixels arranged in a hexagonal lattice structure. The sensor has unit pixel dimensions of 18...
Show moreIn this thesis we report a VLSI design implementation of an application specific, full-frame architecture CCD image sensor for a handwritten Optical Character Recognition system. The design is targeted to the MOSIS 2mu, 2-poly/ 2-metal n-buried channel CCD/CMOS technology. The front side illuminated CCD image sensor uses a transparent polysilicon gate structure and is comprised of 84 (H) x 100 (V) pixels arranged in a hexagonal lattice structure. The sensor has unit pixel dimensions of 18 lambda (H) x 16 lambda (V). A second layer of metal is used for shielding certain areas from incident light, and the effective pixel photosite area is 8 lambda x 8 lambda. The imaging pixels use a 3-phase structure (with an innovative addressing scheme for the hexagonal lattice) for image sensing and horizontal charge shift. Columns of charge are shifted into the vertical 2-phase CCD shift registers, which shift the charge out serially at high speed. The chip has been laid out on the 'tinychip' (2250 mu m x 2220 (mu m) pad frame and fabrication through MOSIS is planned next.
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Date Issued: 1995
PURL: http://purl.flvc.org/fcla/dt/15123
Subject Headings: Integrated circuits--Very large scale integration, Optical character recognition devices, Pattern recognition systems, Imaging systems
Format: Document (PDF)

Title: A VLSI implementable thinning algorithm.
Creator: Zhang, Wei, Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Thinning is a very important step in a Character Recognition System. This thesis evolves a thinning algorithm that can be hardware implemented to improve the speed of the process. The software thinning algorithm features a simple set of rules that can be applied on both hexagonal and orthogonal character images. The hardware architecture features the SIMD structure, simple processing elements and near neighbor communications. The algorithm was simulated against the U.S. Postal Service...
Show moreThinning is a very important step in a Character Recognition System. This thesis evolves a thinning algorithm that can be hardware implemented to improve the speed of the process. The software thinning algorithm features a simple set of rules that can be applied on both hexagonal and orthogonal character images. The hardware architecture features the SIMD structure, simple processing elements and near neighbor communications. The algorithm was simulated against the U.S. Postal Service Character Database. The architecture, evolved with consideration of both the software constraints and the physical layout limitations, was simulated using VHDL hardware description language. Subsequent to VLSI design and simulations the chip was fabricated. The project provides for a feasibility study in utilizing the parallel processor architecture for the implementation of a parallel image thinning algorithm. It is hoped that such a hardware implementation will speed up the processing and lead eventually to a real time system.
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Date Issued: 1992
PURL: http://purl.flvc.org/fcla/dt/14837
Subject Headings: Optical character recognition devices--Computer simulation, Algorithms, Integrated circuits--Very large scale integration
Format: Document (PDF)

Title: Intelligent cache management techniques.
Creator: Jaouhar, Charif., Florida Atlantic University, Mahgoub, Imad
Abstract/Description: This thesis introduced two allocation schemes for cache memory in multiprogramming environments. The proposed schemes, called static and dynamic cache partitioning, are slight variations of the schemes proposed by Thiebaut and Stone. We developed a trace driven simulation program to study and compare the performance of the proposed schemes to that of the cache sharing and cache flushing schemes. Furthermore, we proposed a new replacement technique that uses some heuristic to detect loop...
Show moreThis thesis introduced two allocation schemes for cache memory in multiprogramming environments. The proposed schemes, called static and dynamic cache partitioning, are slight variations of the schemes proposed by Thiebaut and Stone. We developed a trace driven simulation program to study and compare the performance of the proposed schemes to that of the cache sharing and cache flushing schemes. Furthermore, we proposed a new replacement technique that uses some heuristic to detect loop structures in the reference patterns. Initially, the proposed technique uses the Least Recently Used (LRU) strategy. Once a loop has been detected, all the instructions, which will harm performance if they were to be stored in the cache, will be dynamically excluded from being cached. The LRU strategy will resume as soon as the end of the loop has been detected. We have also developed a simulation program to compare the performance of this scheme to that of other related ones, so as to demonstrate its effectiveness. The results show our scheme outperforms the others, especially when the system references are loop dominated.
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Date Issued: 1993
PURL: http://purl.flvc.org/fcla/dt/14973
Subject Headings: Cache memory, Memory hierarchy (Computer science), Integrated circuits--Very large scale integration
Format: Document (PDF)

Title: Parallel architectures and algorithms for digital filter VLSI implementation.
Creator: Desai, Pratik Vishnubhai., Florida Atlantic University, Sudhakar, Raghavan
Abstract/Description: In many scientific and signal processing applications, there are increasing demands for large volume and high speed computations, which call for not only high-speed low power computing hardware, but also for novel approaches in developing new algorithms and architectures. This thesis is concerned with the development of such architectures and algorithms suitable for the VLSI implementation of recursive and nonrecursive 1-dimension digital filters using multiple slower processing elements. As...
Show moreIn many scientific and signal processing applications, there are increasing demands for large volume and high speed computations, which call for not only high-speed low power computing hardware, but also for novel approaches in developing new algorithms and architectures. This thesis is concerned with the development of such architectures and algorithms suitable for the VLSI implementation of recursive and nonrecursive 1-dimension digital filters using multiple slower processing elements. As the background for the development, vectorization techniques such as state-space modeling, block processing, and look ahead computation are introduced. Concurrent architectures such as systolic arrays, wavefront arrays and appropriate parallel filter realizations such as lattice, all-pass, and wave filters are reviewed. A fully hardware efficient systolic array architecture termed as Multiplexed Block-State Filter is proposed for the high speed implementation of lattice and direct realizations of digital filters. The thesis also proposes a new simplified algorithm, Alternate Pole Pairing Algorithm, for realizing an odd order recursive filter as the sum of two all-pass filters. Performance of the proposed schemes are verified through numerical examples and simulation results.
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Date Issued: 1995
PURL: http://purl.flvc.org/fcla/dt/15155
Subject Headings: Integrated circuits--Very large scale integration, Parallel processing (Electronic computers), Computer network architectures, Algorithms (Data processing), Digital integrated circuits
Format: Document (PDF)

Title: CMOS VLSI Design of a Bluetooth™ Receiver Front-End: Performance Evaluation via ADS™-Based Simulations.
Creator: Talbot, Bethany J., Neelakanta, Perambur S., Florida Atlantic University, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: The research addressed and deliberated in this thesis refers to CMOS VLSI design approach of a Bluetooth™ receiver front-end. The performance outcome o f the design is verified with ADS™ RF simulation tool. Essentially the thesis offers an outline on the Bluetooth™ technology and its RF front-end component requirements. The relevant specifications of the designed front-end blocks are identified and are in concurrence with CMOS technology based topologies. For each block identified, both...
Show moreThe research addressed and deliberated in this thesis refers to CMOS VLSI design approach of a Bluetooth™ receiver front-end. The performance outcome o f the design is verified with ADS™ RF simulation tool. Essentially the thesis offers an outline on the Bluetooth™ technology and its RF front-end component requirements. The relevant specifications of the designed front-end blocks are identified and are in concurrence with CMOS technology based topologies. For each block identified, both circuit parameters and device characteristics are chosen as per available design formulations and empirical results in open literature. Specifically, the topology sections designed include antenna input matching, transmit/receive switch, necessary filters, low noise amplifier, mixer and phase lock loop units. The numerical TM, (designed) circuit parameters are duly addressed in appropriate ADS simulation tools and performance evaluations are conducted. Observed results including any deviations are identified and reported. The thesis concludes with a summary and indicates direction for future work.
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Date Issued: 2007
PURL: http://purl.flvc.org/fau/fd/FA00012559
Subject Headings: Integrated circuits--Very large scale integration--Design and construction, Metal oxide semiconductors, Complementary, Bluetooth technology, Network performance (Telecommunication)
Format: Document (PDF)

Title: Enhanced Fibonacci Cubes.
Creator: Qian, Haifeng., Florida Atlantic University, Wu, Jie, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: We propose the enhanced Fibonacci cube (EFC), which is defined based on the sequence Fn = 2(n-2) + 2F(n-4). We study its topological properties, embeddings, applications, routings, VLSI/WSI implementations, and its extensions. Our results show that EFC retains many properties of the hypercube. It contains the Fibonacci cube (FC) and extended Fibonacci cube of the same order as subgraphs and maintains virtually all the desirable properties of FC. EFC is even better in some structural...
Show moreWe propose the enhanced Fibonacci cube (EFC), which is defined based on the sequence Fn = 2(n-2) + 2F(n-4). We study its topological properties, embeddings, applications, routings, VLSI/WSI implementations, and its extensions. Our results show that EFC retains many properties of the hypercube. It contains the Fibonacci cube (FC) and extended Fibonacci cube of the same order as subgraphs and maintains virtually all the desirable properties of FC. EFC is even better in some structural properties, embeddings, applications and VLSI designs than FC or hypercube. With EFC, there are more cubes with various structures and sizes for selection, and more backup cubes into which faulty hypercubes can be reconfigured, which alleviates the size limitation of the hypercube and results in a higher level of fault tolerance.
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Date Issued: 1995
PURL: http://purl.flvc.org/fcla/dt/15196
Subject Headings: Integrated circuits--Very large scale integration, Hypercube networks (Computer networks), Algorithms, Fault-tolerant computing, Multiprocessors
Format: Document (PDF)

Title: System level simulations of an optical character recognition system.
Creator: Phadnis, Mangirish Jayawant., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Optical Character Recognition systems have many applications in today's world of electronic computing. Various software implementations are currently being used. This thesis evolves a massively parallel hardware implementation for the system that is VLSI scaleable and may lead to substantial increase in the processing speed. This system involves various stages for preprocessing and processing of the image implemented with SIMD architecture, using simple processing elements and near neighbor...
Show moreOptical Character Recognition systems have many applications in today's world of electronic computing. Various software implementations are currently being used. This thesis evolves a massively parallel hardware implementation for the system that is VLSI scaleable and may lead to substantial increase in the processing speed. This system involves various stages for preprocessing and processing of the image implemented with SIMD architecture, using simple processing elements and near neighbor communications. The architecture evolved is simulated using the Verilog Hardware Description Language. This project should provide a framework for a massively parallel processing architecture for such systems. It is expected that this project will lead to the design and implementation of a real time system.
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Date Issued: 1994
PURL: http://purl.flvc.org/fcla/dt/15106
Subject Headings: Optical character recognition devices, Integrated circuits--Very large scale integration, Optical scanners, Image processing--Digital techniques
Format: Document (PDF)

Title: Analysis of a novel class of fault-tolerant multistage interconnection networks.
Creator: Huang, Chien-Jen, Florida Atlantic University, Mahgoub, Imad, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Multistage interconnection networks (MINs) have become an important subset of the interconnection networks which are used to communicate between processors and memory modules for large scale multiprocessor systems. Unfortunately, unique path MINs lack fault tolerance. In this dissertation, a novel scheme for constructing fault-tolerant MINs is presented. We first partition the given MINs into even sized partitions and show some fault-tolerant properties of the partitioned MINs. Using three...
Show moreMultistage interconnection networks (MINs) have become an important subset of the interconnection networks which are used to communicate between processors and memory modules for large scale multiprocessor systems. Unfortunately, unique path MINs lack fault tolerance. In this dissertation, a novel scheme for constructing fault-tolerant MINs is presented. We first partition the given MINs into even sized partitions and show some fault-tolerant properties of the partitioned MINs. Using three stages of multiplexers/demultiplexers, an augmenting scheme which takes advantage of locality in program execution is then proposed to further improve the fault-tolerant ability and performance of the partitioned MINs. The topological characteristics of augmented partitioned multistage interconnection networks (APMINs) are analyzed. Based on switch fault model, simulations have been carried out to evaluate the full access and dynamic full access capabilities of APMINs. The results show that the proposed scheme significantly improves the fault-tolerant capability of MINs. Cost effectiveness of this new scheme in terms of cost, full access, dynamic full access, locality, and average path length has also been evaluated. It has been shown that this new scheme is more cost effective for high switch failure rate and/or large size networks. Analytical modeling techniques have been developed to evaluate the performance of AP-Omega network and AP-Omega network-based multiprocessor systems. The performance of Omega, modified Omega, and AP-Omega networks in terms of processor utilization and processor waiting time have been compared and the results show that the new scheme indeed, improves the performance both in network level and in system level. Finally, based on the reliability of serial/parallel network components, models for evaluating the terminal reliability and the network reliability of AP-Omega network using upper and lower bound measures have also been proposed and the results show that applying locality improve APMINs' reliability.
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Date Issued: 1993
PURL: http://purl.flvc.org/fcla/dt/12345
Subject Headings: Integratged circuits--Very large scale integration, Fault-tolerant computing, Computer architecture, Parallel processing (Electronic computers)
Format: Document (PDF)

Title: Design ofMOSFET ultra-wideband low noise amplifiers.
Creator: Camacho, Esteban, Bagby, Jonathan S., Florida Atlantic University
Abstract/Description: Ultra-Wide band (UWB) systems are a new wireless technology capable of transmitting data over a wide spectrum of frequency bands with very low power and high data rates. This technology has the potential to replace almost every cable at home or in an office with a wireless connection. In a UWB receiver, a radio frequency (RF) low noise amplifier (LNA) is one of the most important components. This thesis discusses the entire process involving the design ofUWB low noise amplifiers including a...
Show moreUltra-Wide band (UWB) systems are a new wireless technology capable of transmitting data over a wide spectrum of frequency bands with very low power and high data rates. This technology has the potential to replace almost every cable at home or in an office with a wireless connection. In a UWB receiver, a radio frequency (RF) low noise amplifier (LNA) is one of the most important components. This thesis discusses the entire process involving the design ofUWB low noise amplifiers including a detailed stage by stage analysis of a computer aided design (CAD) of a MOSFET UWB LNA. Simulation tools and concepts from Level I equations are used in order to design a circuit with a realistic MOS model such as the BSIM3 used in this work. The LNA shows improved power consumption over the designs it is based on while still producing comparable results.
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Date Issued: 2008
PURL: http://purl.flvc.org/fau/fd/FA00012510
Subject Headings: Electronic circuit design, Integrated circuits--Very large scale integration, Metal-oxide semiconductor field-effect transistors--Design, Power transistors--Design
Format: Document (PDF)

Title: A VLSI implementable learning algorithm.
Creator: Ruiz, Laura V., Florida Atlantic University, Pandya, Abhijit S., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: A top-down design methodology using hardware description languages (HDL's) and powerful design, analysis, synthesis and layout software tools for electronic circuit design is described and applied to the design of a single layer artificial neural network that incorporates on-chip learning. Using the perception learning algorithm, these simple neurons learn a classification problem in 10.55 microseconds in one application. The objective is to describe a methodology by following the design of a...
Show moreA top-down design methodology using hardware description languages (HDL's) and powerful design, analysis, synthesis and layout software tools for electronic circuit design is described and applied to the design of a single layer artificial neural network that incorporates on-chip learning. Using the perception learning algorithm, these simple neurons learn a classification problem in 10.55 microseconds in one application. The objective is to describe a methodology by following the design of a simple network. This methodology is later applied in the design of a novel architecture, a stochastic neural network. All issues related to algorithmic design for VLSI implementability are discussed and results of layout and timing analysis given over software simulations. A top-down design methodology is presented, including a brief introduction to HDL's and an overview of the software tools used throughout the design process. These tools make it possible now for a designer to complete a design in a relative short period of time. In-depth knowledge of computer architecture, VLSI fabrication, electronic circuits and integrated circuit design is not fundamental to accomplish a task that a few years ago would have required a large team of specialized experts in many fields. This may appeal to researchers from a wide background of knowledge, including computer scientists, mathematicians, and psychologists experimenting with learning algorithms. It is only in a hardware implementation of artificial neural network learning algorithms that the true parallel nature of these architectures could be fully tested. Most of the applications of neural networks are basically software simulations of the algorithms run on a single CPU executing sequential simulations of a parallel, richly interconnected architecture. This dissertation describes a methodology whereby a researcher experimenting with a known or new learning algorithm will be able to test it as it was intentionally designed for, on a parallel hardware architecture.
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Date Issued: 1996
PURL: http://purl.flvc.org/fcla/dt/12453
Subject Headings: Integrated circuits--Very large scale integration--Design and construction, Neural networks (Computer science)--Design and construction, Computer algorithms, Machine learning
Format: Document (PDF)

Title: DCVS logic synthesis.
Creator: Xiao, Kang., Florida Atlantic University, Barrett, Raymond L. Jr., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Implementation of CMOS combinational logic with Differential Cascode Voltage Switch logic (DCVS) may have many advantages over the traditional CMOS logic approaches with respect to device count, layout density and timing. DCVS is an ideal target technology for a logic synthesis system in that it provides a complete function cover by providing the function and its complement simultaneously. DCVS is also more testable due to this. We have developed for IBM's DCVS technology a synthesis...
Show moreImplementation of CMOS combinational logic with Differential Cascode Voltage Switch logic (DCVS) may have many advantages over the traditional CMOS logic approaches with respect to device count, layout density and timing. DCVS is an ideal target technology for a logic synthesis system in that it provides a complete function cover by providing the function and its complement simultaneously. DCVS is also more testable due to this. We have developed for IBM's DCVS technology a synthesis algorithm and a new test generation approach, that are based on topologies rather than individual logic functions. We have found that 19 and 363 DCVS topologies can represent 256 and 65,536 functions, respectively, for the 3- and 4-varaible cases. Physical defect analysis was conducted with the aid of a building block approach to analyze the n-type logic tree and provides a basis for evolving hierarchical test pattern generation for the topologies.
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Date Issued: 1992
PURL: http://purl.flvc.org/fcla/dt/14850
Subject Headings: Integrated circuits--Very large scale integration--Data processing, Metal oxide semiconductors, Complementary, Computer-aided design, Electronic systems, Logic design--Data processing
Format: Document (PDF)

Integrated circuits--Very large scale integration (10)	+ -
Algorithms (3)	+ -
Computer architecture (2)	+ -
Fault-tolerant computing (2)	+ -
Integrated circuits--Very large scale integration--Design and construction (2)	+ -

Metal oxide semiconductors, Complementary (2)	+ -
Optical character recognition devices (2)	+ -
Parallel processing (Electronic computers) (2)	+ -
Algorithms (Data processing) (1)	+ -
Bluetooth technology (1)	+ -
Cache memory (1)	+ -
Computational complexity (1)	+ -
Computer algorithms (1)	+ -
Computer graphics (1)	+ -
Computer network architectures (1)	+ -
Computer-aided design (1)	+ -
Digital integrated circuits (1)	+ -
Electronic circuit design (1)	+ -
Electronic systems (1)	+ -
Graph theory (1)	+ -
Hypercube networks (Computer networks) (1)	+ -
Image processing--Digital techniques (1)	+ -
Imaging systems (1)	+ -
Integrated circuits -- Very large scale integration (1)	+ -
Integrated circuits--Very large scale integration--Data processing (1)	+ -
Integratged circuits--Very large scale integration (1)	+ -
Logic design--Data processing (1)	+ -
Machine learning (1)	+ -
Mathematical optimization (1)	+ -
Memory hierarchy (Computer science) (1)	+ -

Florida Atlantic University (15)	+ -
College of Engineering and Computer Science (11)	+ -
Department of Computer and Electrical Engineering and Computer Science (11)	+ -
Shankar, Ravi (6)	+ -
Mahgoub, Imad (2)	+ -

Bagby, Jonathan S. (1)	+ -
Barrett, Raymond L. Jr. (1)	+ -
Camacho, Esteban (1)	+ -
Charles E. Schmidt College of Science (1)	+ -
Department of Mathematical Sciences (1)	+ -
Desai, Pratik Vishnubhai. (1)	+ -
Gottipati, Chenchu B. (1)	+ -
Horvath, Elizabeth Iren. (1)	+ -
Huang, Chien-Jen (1)	+ -
Jaouhar, Charif. (1)	+ -
Locke, Stephen C. (1)	+ -
Madabushi, Vasudhevan. (1)	+ -
Neelakanta, Perambur S. (1)	+ -
POENATEETAI, VIWAT. (1)	+ -
Pandya, Abhijit S. (1)	+ -
Pesulima, Edward Elisha. (1)	+ -
Phadnis, Mangirish Jayawant. (1)	+ -
Qian, Haifeng. (1)	+ -
Ruiz, Laura V. (1)	+ -
Sudhakar, Raghavan (1)	+ -
Talbot, Bethany J. (1)	+ -
Wu, Jie (1)	+ -
Xiao, Kang. (1)	+ -
Zhang, Wei (1)	+ -

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