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Survey of design techniques for signal integrity
Title
Survey of design techniques for signal integrity.
Creator
Karnati, Raghuveer., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description
Signal Integrity is a major bottleneck for DSM designs. Signal integrity refers to wide variety of problems, which leads to misconception. Signal integrity causes delay or noise at the high-level, but this boils down to resistance, capacitance and inductance (RLC) at circuit level. Several analysis and reduction techniques were proposed for reducing these effects on signal integrity. This work solves the misconception by encompassing different problems Chat effect signal integrity and can be...
Show moreSignal Integrity is a major bottleneck for DSM designs. Signal integrity refers to wide variety of problems, which leads to misconception. Signal integrity causes delay or noise at the high-level, but this boils down to resistance, capacitance and inductance (RLC) at circuit level. Several analysis and reduction techniques were proposed for reducing these effects on signal integrity. This work solves the misconception by encompassing different problems Chat effect signal integrity and can be good reference for a integrated circuit designer. The objective is to analyze these modeling methods, reduction techniques, tools and make recommendations that aids in developing a methodology for perfect design closure with an emphasis on signal integrity. These recommendations would form a basis for developing a methodology to analyze interference effects at higher levels of abstraction.
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Date Issued
2003
PURL
http://purl.flvc.org/fcla/dt/13065
Subject Headings
Integrated circuits--Design and construction, Signal processing, Electronic circuit design
Format
Document (PDF)
An empirical methodology for foundry specific submicroncmos analog circuit design
Title
An empirical methodology for foundry specific submicroncmos analog circuit design.
Creator
Rivas-Torres, Wilfredo, Roth, Zvi S., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description
Analog CMOS amplifiers are the building blocks for many analog circuit applications such as Operational Amplifiers, Comparators, Analog to Digital converters and others. This dissertation presents empirical design methodologies that are both intuitive and easy to follow on how to design these basic building blocks. The design method involves two main phases. In the first phase NMOS and PMOS transistor design kits, provided by a semiconductor foundry, are fully characterized using a set of...
Show moreAnalog CMOS amplifiers are the building blocks for many analog circuit applications such as Operational Amplifiers, Comparators, Analog to Digital converters and others. This dissertation presents empirical design methodologies that are both intuitive and easy to follow on how to design these basic building blocks. The design method involves two main phases. In the first phase NMOS and PMOS transistor design kits, provided by a semiconductor foundry, are fully characterized using a set of simulation experiments. In the second phase the user is capable of modifying all the relevant circuit design parameters while directly observing the tradeoffs in the circuit performance specifications. The final design is a circuit that very closely meets a set of desired design specifications for the design parameters selected. That second phase of the proposed design methodology utilizes a graphical user interface in which the designer moves a series of sliders allowing assessment of various design tradeoffs. The theoretical basis for this design methodology involves the transconductance efficiency and inversion coefficient parameters. In this dissertation there are no restrictive assumptions about the MOS transistor models. The design methodology can be used with any submicron model supported by the foundry process and in this sense the methods included within are general and non-dependent on any specific MOSFET model (e.g. EKV or BSIM3). As part of the design tradeoffs assessment process variations are included during the design process rather than as part of some post-nominal-design analysis. One of the central design parameters of each transistor in the circuit is the MOSFET inversion coefficient. The calculation of the inversion coefficient necessitates the determination of an important process parameter known as the Technology Current. In this dissertation a new method to determine the technology current is developed. Y Parameters are used to characterize the CMOS process and this also helps in improving the technology current determination method. A study of the properties of the technology current proves that indeed a single long channel saturated MOS transistor can be used to determine a fixed technology current value that is used in subsequent submicron CMOS design. Process corners and the variability of the technology current are also studied and the universality of the transconductance efficiency versus inversion coefficient response is shown to be true even in the presence of process variability.
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Date Issued
2013
PURL
http://purl.flvc.org/fau/fd/FA0004050
Subject Headings
Electron transport, Integrated circuits -- Design and construction, Metal oxide semiconductors, Complementary -- Mathematical models
Format
Document (PDF)
low power and high performance centralized full adder
Title
A low power and high performance centralized full adder.
Creator
Srivastav, Sidharth., Florida Atlantic University, Pandya, Abhijit S., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description
In this thesis, we proposed a low power and high performance architecture for 1-bit full adder design. The proposed architecture was proven to offer a wide range of performance ability in terms of power consumption and speed. We implemented the architecture using a 2-input 2 multiplexers, an XOR and an XNOR gate. The proposed architecture and the Standard full adder were designed and simulated using Lasi, Winspice and Silos. Silos, a logic simulation environment was used in the design and...
Show moreIn this thesis, we proposed a low power and high performance architecture for 1-bit full adder design. The proposed architecture was proven to offer a wide range of performance ability in terms of power consumption and speed. We implemented the architecture using a 2-input 2 multiplexers, an XOR and an XNOR gate. The proposed architecture and the Standard full adder were designed and simulated using Lasi, Winspice and Silos. Silos, a logic simulation environment was used in the design and verification of the proposed architecture and the standard full adder that were modeled with Verilog hardware description language. Lasi was used for the layout design of the proposed architecture and the standard full adder. After the layout, both the architectures were compiled separately using LASICKT and a corresponding .CIR file was generated. The .CIR file was imported and executed into WINSPICE3 for the simulation of the circuit.
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Date Issued
2004
PURL
http://purl.flvc.org/fcla/dt/13188
Subject Headings
Digital integrated circuits, Metal oxide semiconductors, Complementary, Integrated circuits--Design and contruction, Verilog (Computer hardware description language), Mixed signal circuits--Design and construction--Computer-aided design
Format
Document (PDF)
Configuration and assessment of hardware-in-the-loop-simulation with high resolution data to coordinate traffic signals
Title
Configuration and assessment of hardware-in-the-loop-simulation with high resolution data to coordinate traffic signals.
Creator
Klanac, Ivica, Stevanovic, Aleksandar, Florida Atlantic University, College of Engineering and Computer Science, Department of Civil, Environmental and Geomatics Engineering
Abstract/Description
Today, the information (signal timings, detector extension, phase sequence, etc.) to install traffic lights on the street are obtained from traffic software simulations platforms, meaning that information from simulation is not tested on the field (intersection where it will be installed) before the installation. Many installed controllers on the street use time of day (TOD) patterns due to cheaper cost than adaptive traffic control systems, but that is not the best solution for traffic...
Show moreToday, the information (signal timings, detector extension, phase sequence, etc.) to install traffic lights on the street are obtained from traffic software simulations platforms, meaning that information from simulation is not tested on the field (intersection where it will be installed) before the installation. Many installed controllers on the street use time of day (TOD) patterns due to cheaper cost than adaptive traffic control systems, but that is not the best solution for traffic volume changes that can occur during the day or even a month. To improve traffic signal operation most of the traffic signal controllers in the same corridor or zone operate in coordination mode. Furthermore, phases need to be in coordination to achieve “green wave”. Green wave is term used when in corridor traffic lights allow continues flow of traffic through intersections that are coordinated.
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Date Issued
2016
PURL
http://purl.flvc.org/fau/fd/FA00004709, http://purl.flvc.org/fau/fd/FA00004709
Subject Headings
Digital control systems, Digital integrated circuits -- Design and construction, Hardware in the loop simulation, Highway engineering -- Safety measures, Traffic engineering -- Technological innovations, Traffic flow -- Management, Traffic signs and signals -- Control systems -- Methodology
Format
Document (PDF)