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- Title
- Debonding failure analysis of overmolded pad array carrier (OMPAC) integrated circuit packages.
- Creator
- Hunt, Stephen Douglas., Florida Atlantic University, Carlsson, Leif A.
- Abstract/Description
-
Recently developed electronic packages called Overmolded Pad Array Chip Carrier (OMPAC) IC packages frequently fail at the interface between the overmold compound and the substrate. In this study, this generic type of structure was evaluated by a combination of experimental and analytical methods. Model specimens representative of OMPAC structures were designed, manufactured and tested to failure. Detailed finite element models of the specimens were developed and analyses conducted to...
Show moreRecently developed electronic packages called Overmolded Pad Array Chip Carrier (OMPAC) IC packages frequently fail at the interface between the overmold compound and the substrate. In this study, this generic type of structure was evaluated by a combination of experimental and analytical methods. Model specimens representative of OMPAC structures were designed, manufactured and tested to failure. Detailed finite element models of the specimens were developed and analyses conducted to calculate debond stresses. Analytical methods were refined to include the effect of stress singularities. Stress results were averaged over a distance of.010 in. around the stress singularities to capture the intensity of the stress. These results were used in a combined stress failure criterion to calculate interfacial strengths based on macroscopic failure loads. The interfacial strengths were found to approach, but not exceed, those of the bulk overmold compound.
Show less - Date Issued
- 1991
- PURL
- http://purl.flvc.org/fcla/dt/14778
- Subject Headings
- Thermal stresses, Integrated circuits
- Format
- Document (PDF)
- Title
- Analysis and minimization of crosstalk in high-speed microstrip transmission lines.
- Creator
- Lu, Lin., Florida Atlantic University, Ungvichian, Vichate, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
- Abstract/Description
-
In printed circuits employing high-speed digital circuits, the interconnects can be considered as transmission lines. The dispersion effects in signals transmitted via such interconnects are of importance in crosstalk phenomena inasmuch as the amount of interline coupling (or crosstalk) in a symmetric, coupled microstrip version of interconnect depends on the difference between the frequency-dependent propagation constants pertinent to even and odd modes of lines. This dissertation is...
Show moreIn printed circuits employing high-speed digital circuits, the interconnects can be considered as transmission lines. The dispersion effects in signals transmitted via such interconnects are of importance in crosstalk phenomena inasmuch as the amount of interline coupling (or crosstalk) in a symmetric, coupled microstrip version of interconnect depends on the difference between the frequency-dependent propagation constants pertinent to even and odd modes of lines. This dissertation is concerned with the studies on the distortion and coupling of transient signals propagating in a symmetric, coupled and lossy (dispersive) microstrip transmission lines. Both time as well as frequency domain characteristics are analyzed and relevant mathematical expressions are obtained vis-a-vis pulse signals on signal lines and coupling on sense lines. Fourier transform technique (FT) and spectral domain approach (SDA) are the methods used in the studies pursued. Specifically, an optimization technique to minimize crosstalk in multilayered, multitrace microstrip lines is developed. Typical simulation results are finished which indicate the feasibility of achieving a crosstalk reduction by 76% at a given distance of 40 mm from the source-end excited with a 25 picosecond gaussian pulse by optimization of the geometry of the structure appropriately. This technique is a new strategy for optimal design of high-speed, digital interconnections on a printed circuit board (PCB). The anomalous behavior of the crosstalk versus the pulse-width of a high-speed digital signal in a closely-spaced, parallel coupled microstrip line is presented. It is shown that depending on the pulse-width of a pulse signal, the space between two lines must be beyond a certain limit for a given strip-width (w) and strip-thickness (h) so that crosstalk can be reduced by spacing lines away. The relevant analysis indicates plausible reasons which cause the said anomalous characteristics of crosstalk. A transient signal propagating on a multilayered, coupled microstrip line with lossy substrates is characterized. Relevant computational algorithm is presented. The Cole-Cole diagrams depicting the odd and even mode complex permittivity versus frequency are evolved. The concept of Cole-Cole representation is applied to analyze crosstalk in a microstrip line. Typical simulations show some very interesting and useful results. This study is the first of its kind and has not been done earlier. Lastly, relevant to above research, logical inferences and conclusions are enumerated and the scope for future research is presented.
Show less - Date Issued
- 1996
- PURL
- http://purl.flvc.org/fcla/dt/12480
- Subject Headings
- Microwave integrated circuits, Strip transmission lines, Crosstalk
- Format
- Document (PDF)
- Title
- Novel multiplexer-based architectures for full adder design.
- Creator
- Al-Sheraidah, Abdulkarim K., Florida Atlantic University, Wang, Yuke
- Abstract/Description
-
We propose five new Multiplexer-Based architectures for 1-bit full adder design. Using a 2-transistors multiplexer gate to implement the first architecture, we are able to produce a 12-transistor full adder cell, Comparing it to four different 10-transistors low-power full adder cells reported previously in literature, the new adder cell named MBA1-12T out performs all of them in power consumption and speed. By implementing those architectures using the 2-input CMOS multiplexer with pass...
Show moreWe propose five new Multiplexer-Based architectures for 1-bit full adder design. Using a 2-transistors multiplexer gate to implement the first architecture, we are able to produce a 12-transistor full adder cell, Comparing it to four different 10-transistors low-power full adder cells reported previously in literature, the new adder cell named MBA1-12T out performs all of them in power consumption and speed. By implementing those architectures using the 2-input CMOS multiplexer with pass-gates, five new high-performance full adder cells are obtained. Those new adder cells are tested along with the conventional 28-transistor CMOS adder cell. Testing results shows that the new adder cells have higher speed and lower power delay product values than the conventional 28-transistor CMOS adder cell.
Show less - Date Issued
- 2000
- PURL
- http://purl.flvc.org/fcla/dt/12667
- Subject Headings
- Metal oxide semiconductors, Complementary, Digital integrated circuits
- Format
- Document (PDF)
- Title
- Measurements of output factors for small photon fields up to 10 cm x 10 cm.
- Creator
- Bacala, Angelina, Pella, Silvia, Charles E. Schmidt College of Science, Department of Physics
- Abstract/Description
-
Field output factors (OF) for photon beams from a 6 MV medical accelerator were measured using five different detectors in a scanning water phantom. The measurements were taken for square field sizes of integral widths ranging from 1 cm to 10 cm for two reference source-to-surface distances (SSD) and depths in water. For the diode detectors, square field widths as small as 2.5 mm were also studied. The photon beams were collimated by using either the jaws or the multileaf collimators....
Show moreField output factors (OF) for photon beams from a 6 MV medical accelerator were measured using five different detectors in a scanning water phantom. The measurements were taken for square field sizes of integral widths ranging from 1 cm to 10 cm for two reference source-to-surface distances (SSD) and depths in water. For the diode detectors, square field widths as small as 2.5 mm were also studied. The photon beams were collimated by using either the jaws or the multileaf collimators. Measured OFs are found to depend upon the field size, SSD, depth and also upon the type of beam collimation, size and type of detector used. For field sizes larger than 3 cm x 3 cm, the OF measurements agree to within 1% or less. The largest variation in OF occurs for jawsshaped field of size 1 cm x 1cm, where a difference of more than 18% is observed.
Show less - Date Issued
- 2013
- PURL
- http://purl.flvc.org/fau/fd/FA0004003
- Subject Headings
- Integrated circuits, Photonics, Quantum electrodynamics, Quantum theory
- Format
- Document (PDF)
- Title
- PIREN(copyright): A heuristic algorithm for standard cell placement.
- Creator
- Horvath, Elizabeth Iren., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
- Abstract/Description
-
The placement problem is an important part in the design process of VLSI chips. It is necessary to have a proper placement so that all connections between modules in a chip can be routed in a minimum area without violating any physical or electrical constraints. Current algorithms either do not give optimum solutions, are computationally slow, or are difficult to parallelize. PIREN(copyright) is a parallel implementation of a force directed algorithm which seeks to overcome the large amount...
Show moreThe placement problem is an important part in the design process of VLSI chips. It is necessary to have a proper placement so that all connections between modules in a chip can be routed in a minimum area without violating any physical or electrical constraints. Current algorithms either do not give optimum solutions, are computationally slow, or are difficult to parallelize. PIREN(copyright) is a parallel implementation of a force directed algorithm which seeks to overcome the large amount of computer time associated with solving the placement problem. Each active processor in the massively parallel SIMD machine, the MasPar MP-2.2, can perform in parallel the computation necessary to place cells in an optimum location relative to one another based upon the connectivity between cells. This is due to a salient feature of the serial algorithm which allows multiple permutations to be made simultaneously on all modules in order to minimize the objective function. The serial implementation of PIREN(copyright) compares favorably in both run time and layout quality to the simulated annealing based algorithm, TimberWolf3.2$\sp\copyright$. The parallel implementation on the MP-2.2 has a speedup of 4.5 to 58.0 over the serial version of PIREN$\sp\copyright$ running of the VAX 6320, while producing layouts for several MCNC benchmarks which are of the same quality as those produced by the serial implementation.
Show less - Date Issued
- 1992
- PURL
- http://purl.flvc.org/fcla/dt/12301
- Subject Headings
- Integrated circuits--Very large scale integration, Algorithms
- Format
- Document (PDF)
- Title
- SEMI-CUSTOM DESIGN OF A MICROPROGRAMMED TESTABLE REDUCED INSTRUCTION SET COMPUTER.
- Creator
- POENATEETAI, VIWAT., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
- Abstract/Description
-
The concept of a Reduced Instruction Set Computer (RISC) has evolved out of a desire to enhance the performance of a computer. We present here a detailed design of a Testable Reduced Instruction Set Computer (TRISC) that utilizes a Multiple Register Set. Level Sensitive Scan Design (LSSD) is used to incorporate testability into our design. We first evolved a functional description of the design using Digital Design Language (DDL) a hardware programming language. We then entered the schematic...
Show moreThe concept of a Reduced Instruction Set Computer (RISC) has evolved out of a desire to enhance the performance of a computer. We present here a detailed design of a Testable Reduced Instruction Set Computer (TRISC) that utilizes a Multiple Register Set. Level Sensitive Scan Design (LSSD) is used to incorporate testability into our design. We first evolved a functional description of the design using Digital Design Language (DDL) a hardware programming language. We then entered the schematic of the design into Daisy's Logician V, a CAD/CAE workstation, using NCR CMOSII Digital Standard Cell Library. We then performed a unit delay simulation on the hierarchical design database to ascertain the logical functioning of the system.
Show less - Date Issued
- 1986
- PURL
- http://purl.flvc.org/fcla/dt/14284
- Subject Headings
- Computer architecture, Integrated circuits--Very large scale integration
- Format
- Document (PDF)
- Title
- Design of 10-transistor low-power full adders.
- Creator
- Bui, Hung Tien., Florida Atlantic University, Wang, Yuke
- Abstract/Description
-
We propose two approaches to design 1-bit full adders which can yield good performance at low power consumption. In the first approach, we design XOR/XNOR gates using a minimal number of CMOS transistors. Comparing with 10 different XOR/XNOR gates reported in literature, the new XOR/XNOR gates consume less power. The gates consisting of the smallest number of transistors are combined to create 1-bit full adders. The process is systematic and yields a total of 42 10-transistor full adders, 41...
Show moreWe propose two approaches to design 1-bit full adders which can yield good performance at low power consumption. In the first approach, we design XOR/XNOR gates using a minimal number of CMOS transistors. Comparing with 10 different XOR/XNOR gates reported in literature, the new XOR/XNOR gates consume less power. The gates consisting of the smallest number of transistors are combined to create 1-bit full adders. The process is systematic and yields a total of 42 10-transistor full adders, 41 of which are new. Simulation results show that most of the new adders perform better than a previously existing 10-transistor adder and a complementary CMOS adder in terms of power and speed with heavier load. Three adders consistently perform better. In the second approach, we utilized a method called the centralized design to create four new 10-transistor full adders. Simulation results show that these new adders perform better than the previously existing 10-transistor and the complementary CMOS adder.
Show less - Date Issued
- 2000
- PURL
- http://purl.flvc.org/fcla/dt/15759
- Subject Headings
- Digital integrated circuits, Low voltage integrated circuits, Metal oxide semiconductors, Complementary
- Format
- Document (PDF)
- Title
- Digital implementation issues of artificial neural networks.
- Creator
- Pesulima, Edward Elisha., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
- Abstract/Description
-
Recent years have seen the renaissance of the neural network field. Significant advances in our understanding of neural networks and its possible applications necessitate investigations into possible implementation strategies. Among the presently available implementation medium, digital VLSI hardware is one of the more promising because of its maturity and availability. We discuss various issues connected with implementing neural networks in digital VLSI hardware. A new sigmoidal transfer...
Show moreRecent years have seen the renaissance of the neural network field. Significant advances in our understanding of neural networks and its possible applications necessitate investigations into possible implementation strategies. Among the presently available implementation medium, digital VLSI hardware is one of the more promising because of its maturity and availability. We discuss various issues connected with implementing neural networks in digital VLSI hardware. A new sigmoidal transfer function is proposed with that implementation in mind. Possible realizations of the function for stochastic and deterministic neural networks are discussed. Simulation studies of applying neural networks in constraint optimization and learning problems are carried out. These simulations were performed strictly in integer arithmetic. Simulation results provides an encouraging outlook for implementing these neural network applications in digital VLSI hardware. Important results concerning the sizes of various network values were found for learning algorithms.
Show less - Date Issued
- 1990
- PURL
- http://purl.flvc.org/fcla/dt/14646
- Subject Headings
- Neural computers, Neural computers--Circuits, Integrated circuits--Very large scale integration
- Format
- Document (PDF)
- Title
- Parallel architectures and algorithms for digital filter VLSI implementation.
- Creator
- Desai, Pratik Vishnubhai., Florida Atlantic University, Sudhakar, Raghavan
- Abstract/Description
-
In many scientific and signal processing applications, there are increasing demands for large volume and high speed computations, which call for not only high-speed low power computing hardware, but also for novel approaches in developing new algorithms and architectures. This thesis is concerned with the development of such architectures and algorithms suitable for the VLSI implementation of recursive and nonrecursive 1-dimension digital filters using multiple slower processing elements. As...
Show moreIn many scientific and signal processing applications, there are increasing demands for large volume and high speed computations, which call for not only high-speed low power computing hardware, but also for novel approaches in developing new algorithms and architectures. This thesis is concerned with the development of such architectures and algorithms suitable for the VLSI implementation of recursive and nonrecursive 1-dimension digital filters using multiple slower processing elements. As the background for the development, vectorization techniques such as state-space modeling, block processing, and look ahead computation are introduced. Concurrent architectures such as systolic arrays, wavefront arrays and appropriate parallel filter realizations such as lattice, all-pass, and wave filters are reviewed. A fully hardware efficient systolic array architecture termed as Multiplexed Block-State Filter is proposed for the high speed implementation of lattice and direct realizations of digital filters. The thesis also proposes a new simplified algorithm, Alternate Pole Pairing Algorithm, for realizing an odd order recursive filter as the sum of two all-pass filters. Performance of the proposed schemes are verified through numerical examples and simulation results.
Show less - Date Issued
- 1995
- PURL
- http://purl.flvc.org/fcla/dt/15155
- Subject Headings
- Integrated circuits--Very large scale integration, Parallel processing (Electronic computers), Computer network architectures, Algorithms (Data processing), Digital integrated circuits
- Format
- Document (PDF)
- Title
- Low-level and high-level correlation for image registration.
- Creator
- Mandalia, Anil Dhirajlal., Florida Atlantic University, Sudhakar, Raghavan, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
- Abstract/Description
-
The fundamental goal of a machine vision system in the inspection of an assembled printed circuit board is to locate the integrated circuit(IC) components. These components are then checked for their position and orientation with respect to a given position and orientation of the model and to detect deviations. To this end, a method based on a modified two-level correlation scheme is presented in this thesis. In the first level, Low-Level correlation, a modified two-stage template matching...
Show moreThe fundamental goal of a machine vision system in the inspection of an assembled printed circuit board is to locate the integrated circuit(IC) components. These components are then checked for their position and orientation with respect to a given position and orientation of the model and to detect deviations. To this end, a method based on a modified two-level correlation scheme is presented in this thesis. In the first level, Low-Level correlation, a modified two-stage template matching method is proposed. It makes use of the random search techniques, better known as the Monte Carlo method, to speed up the matching process on binarized version of the images. Due to the random search techniques, there is uncertainty involved in the location where the matches are found. In the second level, High-Level correlation, an evidence scheme based on the Dempster-Shafer formalism is presented to resolve the uncertainty. Experiment results performed on a printed circuit board containing mounted integrated components is also presented to demonstrate the validity of the techniques.
Show less - Date Issued
- 1990
- PURL
- http://purl.flvc.org/fcla/dt/14635
- Subject Headings
- Image processing--Digital techniques, Computer vision, Integrated circuits
- Format
- Document (PDF)
- Title
- Survey of design techniques for signal integrity.
- Creator
- Karnati, Raghuveer., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
- Abstract/Description
-
Signal Integrity is a major bottleneck for DSM designs. Signal integrity refers to wide variety of problems, which leads to misconception. Signal integrity causes delay or noise at the high-level, but this boils down to resistance, capacitance and inductance (RLC) at circuit level. Several analysis and reduction techniques were proposed for reducing these effects on signal integrity. This work solves the misconception by encompassing different problems Chat effect signal integrity and can be...
Show moreSignal Integrity is a major bottleneck for DSM designs. Signal integrity refers to wide variety of problems, which leads to misconception. Signal integrity causes delay or noise at the high-level, but this boils down to resistance, capacitance and inductance (RLC) at circuit level. Several analysis and reduction techniques were proposed for reducing these effects on signal integrity. This work solves the misconception by encompassing different problems Chat effect signal integrity and can be good reference for a integrated circuit designer. The objective is to analyze these modeling methods, reduction techniques, tools and make recommendations that aids in developing a methodology for perfect design closure with an emphasis on signal integrity. These recommendations would form a basis for developing a methodology to analyze interference effects at higher levels of abstraction.
Show less - Date Issued
- 2003
- PURL
- http://purl.flvc.org/fcla/dt/13065
- Subject Headings
- Integrated circuits--Design and construction, Signal processing, Electronic circuit design
- Format
- Document (PDF)
- Title
- Graph labeling and non-separating trees.
- Creator
- Gottipati, Chenchu B., Locke, Stephen C., Florida Atlantic University, Charles E. Schmidt College of Science, Department of Mathematical Sciences
- Abstract/Description
-
This dissertation studies two independent problems, one is about graph labeling and the other problem is related to connectivity condition in a simple graph. Graph labeling is a rapidly developing area of research in graph theory, having connections with a variety of application-oriented areas such as VLSI optimization, data structures and data representation. Furthermore, the connectivity conditions in a simple graphs may help us to study the new aspects of ad hoc networks, social networks...
Show moreThis dissertation studies two independent problems, one is about graph labeling and the other problem is related to connectivity condition in a simple graph. Graph labeling is a rapidly developing area of research in graph theory, having connections with a variety of application-oriented areas such as VLSI optimization, data structures and data representation. Furthermore, the connectivity conditions in a simple graphs may help us to study the new aspects of ad hoc networks, social networks and web graphs. In chapter 2, we study path systems, reduced path systems and how to construct a super edge-graceful tree with any number of edges using path systems. First, we give an algorithm to reduce a labeled path system to a smaller labeled path system of a different type. First, we investigate the cases (m, k) = (3; 5) and (m, k) = (4; 7), where m is the number of paths and 2k is the length of each path, and then we give a generalization for any k, m = 3 and m = 4. We also describe a procedure to construct a super-edge-graceful tree with any number of edges.
Show less - Date Issued
- 2014
- PURL
- http://purl.flvc.org/fau/fd/FA00004289, http://purl.flvc.org/fau/fd/FA00004289
- Subject Headings
- Computational complexity, Computer graphics, Graph theory, Integrated circuits -- Very large scale integration, Mathematical optimization
- Format
- Document (PDF)
- Title
- A VLSI implementation of a hexagonal topology CCD image sensor.
- Creator
- Madabushi, Vasudhevan., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
- Abstract/Description
-
In this thesis we report a VLSI design implementation of an application specific, full-frame architecture CCD image sensor for a handwritten Optical Character Recognition system. The design is targeted to the MOSIS 2mu, 2-poly/ 2-metal n-buried channel CCD/CMOS technology. The front side illuminated CCD image sensor uses a transparent polysilicon gate structure and is comprised of 84 (H) x 100 (V) pixels arranged in a hexagonal lattice structure. The sensor has unit pixel dimensions of 18...
Show moreIn this thesis we report a VLSI design implementation of an application specific, full-frame architecture CCD image sensor for a handwritten Optical Character Recognition system. The design is targeted to the MOSIS 2mu, 2-poly/ 2-metal n-buried channel CCD/CMOS technology. The front side illuminated CCD image sensor uses a transparent polysilicon gate structure and is comprised of 84 (H) x 100 (V) pixels arranged in a hexagonal lattice structure. The sensor has unit pixel dimensions of 18 lambda (H) x 16 lambda (V). A second layer of metal is used for shielding certain areas from incident light, and the effective pixel photosite area is 8 lambda x 8 lambda. The imaging pixels use a 3-phase structure (with an innovative addressing scheme for the hexagonal lattice) for image sensing and horizontal charge shift. Columns of charge are shifted into the vertical 2-phase CCD shift registers, which shift the charge out serially at high speed. The chip has been laid out on the 'tinychip' (2250 mu m x 2220 (mu m) pad frame and fabrication through MOSIS is planned next.
Show less - Date Issued
- 1995
- PURL
- http://purl.flvc.org/fcla/dt/15123
- Subject Headings
- Integrated circuits--Very large scale integration, Optical character recognition devices, Pattern recognition systems, Imaging systems
- Format
- Document (PDF)
- Title
- A VLSI implementable thinning algorithm.
- Creator
- Zhang, Wei, Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
- Abstract/Description
-
Thinning is a very important step in a Character Recognition System. This thesis evolves a thinning algorithm that can be hardware implemented to improve the speed of the process. The software thinning algorithm features a simple set of rules that can be applied on both hexagonal and orthogonal character images. The hardware architecture features the SIMD structure, simple processing elements and near neighbor communications. The algorithm was simulated against the U.S. Postal Service...
Show moreThinning is a very important step in a Character Recognition System. This thesis evolves a thinning algorithm that can be hardware implemented to improve the speed of the process. The software thinning algorithm features a simple set of rules that can be applied on both hexagonal and orthogonal character images. The hardware architecture features the SIMD structure, simple processing elements and near neighbor communications. The algorithm was simulated against the U.S. Postal Service Character Database. The architecture, evolved with consideration of both the software constraints and the physical layout limitations, was simulated using VHDL hardware description language. Subsequent to VLSI design and simulations the chip was fabricated. The project provides for a feasibility study in utilizing the parallel processor architecture for the implementation of a parallel image thinning algorithm. It is hoped that such a hardware implementation will speed up the processing and lead eventually to a real time system.
Show less - Date Issued
- 1992
- PURL
- http://purl.flvc.org/fcla/dt/14837
- Subject Headings
- Optical character recognition devices--Computer simulation, Algorithms, Integrated circuits--Very large scale integration
- Format
- Document (PDF)
- Title
- Intelligent cache management techniques.
- Creator
- Jaouhar, Charif., Florida Atlantic University, Mahgoub, Imad
- Abstract/Description
-
This thesis introduced two allocation schemes for cache memory in multiprogramming environments. The proposed schemes, called static and dynamic cache partitioning, are slight variations of the schemes proposed by Thiebaut and Stone. We developed a trace driven simulation program to study and compare the performance of the proposed schemes to that of the cache sharing and cache flushing schemes. Furthermore, we proposed a new replacement technique that uses some heuristic to detect loop...
Show moreThis thesis introduced two allocation schemes for cache memory in multiprogramming environments. The proposed schemes, called static and dynamic cache partitioning, are slight variations of the schemes proposed by Thiebaut and Stone. We developed a trace driven simulation program to study and compare the performance of the proposed schemes to that of the cache sharing and cache flushing schemes. Furthermore, we proposed a new replacement technique that uses some heuristic to detect loop structures in the reference patterns. Initially, the proposed technique uses the Least Recently Used (LRU) strategy. Once a loop has been detected, all the instructions, which will harm performance if they were to be stored in the cache, will be dynamically excluded from being cached. The LRU strategy will resume as soon as the end of the loop has been detected. We have also developed a simulation program to compare the performance of this scheme to that of other related ones, so as to demonstrate its effectiveness. The results show our scheme outperforms the others, especially when the system references are loop dominated.
Show less - Date Issued
- 1993
- PURL
- http://purl.flvc.org/fcla/dt/14973
- Subject Headings
- Cache memory, Memory hierarchy (Computer science), Integrated circuits--Very large scale integration
- Format
- Document (PDF)
- Title
- Design ofMOSFET ultra-wideband low noise amplifiers.
- Creator
- Camacho, Esteban, Bagby, Jonathan S., Florida Atlantic University
- Abstract/Description
-
Ultra-Wide band (UWB) systems are a new wireless technology capable of transmitting data over a wide spectrum of frequency bands with very low power and high data rates. This technology has the potential to replace almost every cable at home or in an office with a wireless connection. In a UWB receiver, a radio frequency (RF) low noise amplifier (LNA) is one of the most important components. This thesis discusses the entire process involving the design ofUWB low noise amplifiers including a...
Show moreUltra-Wide band (UWB) systems are a new wireless technology capable of transmitting data over a wide spectrum of frequency bands with very low power and high data rates. This technology has the potential to replace almost every cable at home or in an office with a wireless connection. In a UWB receiver, a radio frequency (RF) low noise amplifier (LNA) is one of the most important components. This thesis discusses the entire process involving the design ofUWB low noise amplifiers including a detailed stage by stage analysis of a computer aided design (CAD) of a MOSFET UWB LNA. Simulation tools and concepts from Level I equations are used in order to design a circuit with a realistic MOS model such as the BSIM3 used in this work. The LNA shows improved power consumption over the designs it is based on while still producing comparable results.
Show less - Date Issued
- 2008
- PURL
- http://purl.flvc.org/fau/fd/FA00012510
- Subject Headings
- Electronic circuit design, Integrated circuits--Very large scale integration, Metal-oxide semiconductor field-effect transistors--Design, Power transistors--Design
- Format
- Document (PDF)
- Title
- Imaging through ground-level turbulence by fourier telescopy: simulations and preliminary experiments.
- Creator
- Randunu-Pathirannehelage, Nishantha, Rhodes, William T., Florida Atlantic University, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
- Abstract/Description
-
Fourier telescopy imaging is a recently-developed imaging method that relies on active structured-light illumination of the object. Reflected/scattered light is measured by a large “light bucket” detector; processing of the detected signal yields the magnitude and phase of spatial frequency components of the object reflectance or transmittance function. An inverse Fourier transform results in the image. In 2012 a novel method, known as time-average Fourier telescopy (TAFT), was introduced by...
Show moreFourier telescopy imaging is a recently-developed imaging method that relies on active structured-light illumination of the object. Reflected/scattered light is measured by a large “light bucket” detector; processing of the detected signal yields the magnitude and phase of spatial frequency components of the object reflectance or transmittance function. An inverse Fourier transform results in the image. In 2012 a novel method, known as time-average Fourier telescopy (TAFT), was introduced by William T. Rhodes as a means for diffraction-limited imaging through ground-level atmospheric turbulence. This method, which can be applied to long horizontal-path terrestrial imaging, addresses a need that is not solved by the adaptive optics methods being used in astronomical imaging. Field-experiment verification of the TAFT concept requires instrumentation that is not available at Florida Atlantic University. The objective of this doctoral research program is thus to demonstrate, in the absence of full-scale experimentation, the feasibility of time-average Fourier telescopy through (a) the design, construction, and testing of smallscale laboratory instrumentation capable of exploring basic Fourier telescopy datagathering operations, and (b) the development of MATLAB-based software capable of demonstrating the effect of kilometer-scale passage of laser beams through ground-level turbulence in a numerical simulation of TAFT.
Show less - Date Issued
- 2015
- PURL
- http://purl.flvc.org/fau/fd/FA00004401, http://purl.flvc.org/fau/fd/FA00004401
- Subject Headings
- Fourier analysis, Fourier integral operators, Interconnects (Integrated circuit technology), Remote sensing, Spread spectrum communications, Wireless sensor networks
- Format
- Document (PDF)
- Title
- CMOS VLSI Design of a Bluetooth™ Receiver Front-End: Performance Evaluation via ADS™-Based Simulations.
- Creator
- Talbot, Bethany J., Neelakanta, Perambur S., Florida Atlantic University, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
- Abstract/Description
-
The research addressed and deliberated in this thesis refers to CMOS VLSI design approach of a Bluetooth™ receiver front-end. The performance outcome o f the design is verified with ADS™ RF simulation tool. Essentially the thesis offers an outline on the Bluetooth™ technology and its RF front-end component requirements. The relevant specifications of the designed front-end blocks are identified and are in concurrence with CMOS technology based topologies. For each block identified, both...
Show moreThe research addressed and deliberated in this thesis refers to CMOS VLSI design approach of a Bluetooth™ receiver front-end. The performance outcome o f the design is verified with ADS™ RF simulation tool. Essentially the thesis offers an outline on the Bluetooth™ technology and its RF front-end component requirements. The relevant specifications of the designed front-end blocks are identified and are in concurrence with CMOS technology based topologies. For each block identified, both circuit parameters and device characteristics are chosen as per available design formulations and empirical results in open literature. Specifically, the topology sections designed include antenna input matching, transmit/receive switch, necessary filters, low noise amplifier, mixer and phase lock loop units. The numerical TM, (designed) circuit parameters are duly addressed in appropriate ADS simulation tools and performance evaluations are conducted. Observed results including any deviations are identified and reported. The thesis concludes with a summary and indicates direction for future work.
Show less - Date Issued
- 2007
- PURL
- http://purl.flvc.org/fau/fd/FA00012559
- Subject Headings
- Integrated circuits--Very large scale integration--Design and construction, Metal oxide semiconductors, Complementary, Bluetooth technology, Network performance (Telecommunication)
- Format
- Document (PDF)
- Title
- Enhanced Fibonacci Cubes.
- Creator
- Qian, Haifeng., Florida Atlantic University, Wu, Jie, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
- Abstract/Description
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We propose the enhanced Fibonacci cube (EFC), which is defined based on the sequence Fn = 2(n-2) + 2F(n-4). We study its topological properties, embeddings, applications, routings, VLSI/WSI implementations, and its extensions. Our results show that EFC retains many properties of the hypercube. It contains the Fibonacci cube (FC) and extended Fibonacci cube of the same order as subgraphs and maintains virtually all the desirable properties of FC. EFC is even better in some structural...
Show moreWe propose the enhanced Fibonacci cube (EFC), which is defined based on the sequence Fn = 2(n-2) + 2F(n-4). We study its topological properties, embeddings, applications, routings, VLSI/WSI implementations, and its extensions. Our results show that EFC retains many properties of the hypercube. It contains the Fibonacci cube (FC) and extended Fibonacci cube of the same order as subgraphs and maintains virtually all the desirable properties of FC. EFC is even better in some structural properties, embeddings, applications and VLSI designs than FC or hypercube. With EFC, there are more cubes with various structures and sizes for selection, and more backup cubes into which faulty hypercubes can be reconfigured, which alleviates the size limitation of the hypercube and results in a higher level of fault tolerance.
Show less - Date Issued
- 1995
- PURL
- http://purl.flvc.org/fcla/dt/15196
- Subject Headings
- Integrated circuits--Very large scale integration, Hypercube networks (Computer networks), Algorithms, Fault-tolerant computing, Multiprocessors
- Format
- Document (PDF)
- Title
- System level simulations of an optical character recognition system.
- Creator
- Phadnis, Mangirish Jayawant., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
- Abstract/Description
-
Optical Character Recognition systems have many applications in today's world of electronic computing. Various software implementations are currently being used. This thesis evolves a massively parallel hardware implementation for the system that is VLSI scaleable and may lead to substantial increase in the processing speed. This system involves various stages for preprocessing and processing of the image implemented with SIMD architecture, using simple processing elements and near neighbor...
Show moreOptical Character Recognition systems have many applications in today's world of electronic computing. Various software implementations are currently being used. This thesis evolves a massively parallel hardware implementation for the system that is VLSI scaleable and may lead to substantial increase in the processing speed. This system involves various stages for preprocessing and processing of the image implemented with SIMD architecture, using simple processing elements and near neighbor communications. The architecture evolved is simulated using the Verilog Hardware Description Language. This project should provide a framework for a massively parallel processing architecture for such systems. It is expected that this project will lead to the design and implementation of a real time system.
Show less - Date Issued
- 1994
- PURL
- http://purl.flvc.org/fcla/dt/15106
- Subject Headings
- Optical character recognition devices, Integrated circuits--Very large scale integration, Optical scanners, Image processing--Digital techniques
- Format
- Document (PDF)