Current Search: Integrated circuits -- Design and construction (x)
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- Title
- Survey of design techniques for signal integrity.
- Creator
- Karnati, Raghuveer., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
- Abstract/Description
-
Signal Integrity is a major bottleneck for DSM designs. Signal integrity refers to wide variety of problems, which leads to misconception. Signal integrity causes delay or noise at the high-level, but this boils down to resistance, capacitance and inductance (RLC) at circuit level. Several analysis and reduction techniques were proposed for reducing these effects on signal integrity. This work solves the misconception by encompassing different problems Chat effect signal integrity and can be...
Show moreSignal Integrity is a major bottleneck for DSM designs. Signal integrity refers to wide variety of problems, which leads to misconception. Signal integrity causes delay or noise at the high-level, but this boils down to resistance, capacitance and inductance (RLC) at circuit level. Several analysis and reduction techniques were proposed for reducing these effects on signal integrity. This work solves the misconception by encompassing different problems Chat effect signal integrity and can be good reference for a integrated circuit designer. The objective is to analyze these modeling methods, reduction techniques, tools and make recommendations that aids in developing a methodology for perfect design closure with an emphasis on signal integrity. These recommendations would form a basis for developing a methodology to analyze interference effects at higher levels of abstraction.
Show less - Date Issued
- 2003
- PURL
- http://purl.flvc.org/fcla/dt/13065
- Subject Headings
- Integrated circuits--Design and construction, Signal processing, Electronic circuit design
- Format
- Document (PDF)
- Title
- An empirical methodology for foundry specific submicroncmos analog circuit design.
- Creator
- Rivas-Torres, Wilfredo, Roth, Zvi S., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
- Abstract/Description
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Analog CMOS amplifiers are the building blocks for many analog circuit applications such as Operational Amplifiers, Comparators, Analog to Digital converters and others. This dissertation presents empirical design methodologies that are both intuitive and easy to follow on how to design these basic building blocks. The design method involves two main phases. In the first phase NMOS and PMOS transistor design kits, provided by a semiconductor foundry, are fully characterized using a set of...
Show moreAnalog CMOS amplifiers are the building blocks for many analog circuit applications such as Operational Amplifiers, Comparators, Analog to Digital converters and others. This dissertation presents empirical design methodologies that are both intuitive and easy to follow on how to design these basic building blocks. The design method involves two main phases. In the first phase NMOS and PMOS transistor design kits, provided by a semiconductor foundry, are fully characterized using a set of simulation experiments. In the second phase the user is capable of modifying all the relevant circuit design parameters while directly observing the tradeoffs in the circuit performance specifications. The final design is a circuit that very closely meets a set of desired design specifications for the design parameters selected. That second phase of the proposed design methodology utilizes a graphical user interface in which the designer moves a series of sliders allowing assessment of various design tradeoffs. The theoretical basis for this design methodology involves the transconductance efficiency and inversion coefficient parameters. In this dissertation there are no restrictive assumptions about the MOS transistor models. The design methodology can be used with any submicron model supported by the foundry process and in this sense the methods included within are general and non-dependent on any specific MOSFET model (e.g. EKV or BSIM3). As part of the design tradeoffs assessment process variations are included during the design process rather than as part of some post-nominal-design analysis. One of the central design parameters of each transistor in the circuit is the MOSFET inversion coefficient. The calculation of the inversion coefficient necessitates the determination of an important process parameter known as the Technology Current. In this dissertation a new method to determine the technology current is developed. Y Parameters are used to characterize the CMOS process and this also helps in improving the technology current determination method. A study of the properties of the technology current proves that indeed a single long channel saturated MOS transistor can be used to determine a fixed technology current value that is used in subsequent submicron CMOS design. Process corners and the variability of the technology current are also studied and the universality of the transconductance efficiency versus inversion coefficient response is shown to be true even in the presence of process variability.
Show less - Date Issued
- 2013
- PURL
- http://purl.flvc.org/fau/fd/FA0004050
- Subject Headings
- Electron transport, Integrated circuits -- Design and construction, Metal oxide semiconductors, Complementary -- Mathematical models
- Format
- Document (PDF)
- Title
- An algebraic attack on block ciphers.
- Creator
- Matheis, Kenneth., Charles E. Schmidt College of Science, Department of Mathematical Sciences
- Abstract/Description
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The aim of this work is to investigate an algebraic attack on block ciphers called Multiple Right Hand Sides (MRHS). MRHS models a block cipher as a system of n matrix equations Si := Aix = [Li], where each Li can be expressed as a set of its columns bi1, . . . , bisi . The set of solutions Ti of Si is dened as the union of the solutions of Aix = bij , and the set of solutions of the system S1, . . . , Sn is dened as the intersection of T1, . . . , Tn. Our main contribution is a hardware...
Show moreThe aim of this work is to investigate an algebraic attack on block ciphers called Multiple Right Hand Sides (MRHS). MRHS models a block cipher as a system of n matrix equations Si := Aix = [Li], where each Li can be expressed as a set of its columns bi1, . . . , bisi . The set of solutions Ti of Si is dened as the union of the solutions of Aix = bij , and the set of solutions of the system S1, . . . , Sn is dened as the intersection of T1, . . . , Tn. Our main contribution is a hardware platform which implements a particular algorithm that solves MRHS systems (and hence block ciphers). The case is made that the platform performs several thousand orders of magnitude faster than software, it costs less than US$1,000,000, and that actual times of block cipher breakage can be calculated once it is known how the corresponding software behaves. Options in MRHS are also explored with a view to increase its efficiency.
Show less - Date Issued
- 2010
- PURL
- http://purl.flvc.org/FAU/2976444
- Subject Headings
- Ciphers, Cryptography, Data encryption (Computer science), Computer security, Coding theory, Integrated circuits, Design and construction
- Format
- Document (PDF)
- Title
- CMOS VLSI Design of a Bluetooth™ Receiver Front-End: Performance Evaluation via ADS™-Based Simulations.
- Creator
- Talbot, Bethany J., Neelakanta, Perambur S., Florida Atlantic University, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
- Abstract/Description
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The research addressed and deliberated in this thesis refers to CMOS VLSI design approach of a Bluetooth™ receiver front-end. The performance outcome o f the design is verified with ADS™ RF simulation tool. Essentially the thesis offers an outline on the Bluetooth™ technology and its RF front-end component requirements. The relevant specifications of the designed front-end blocks are identified and are in concurrence with CMOS technology based topologies. For each block identified, both...
Show moreThe research addressed and deliberated in this thesis refers to CMOS VLSI design approach of a Bluetooth™ receiver front-end. The performance outcome o f the design is verified with ADS™ RF simulation tool. Essentially the thesis offers an outline on the Bluetooth™ technology and its RF front-end component requirements. The relevant specifications of the designed front-end blocks are identified and are in concurrence with CMOS technology based topologies. For each block identified, both circuit parameters and device characteristics are chosen as per available design formulations and empirical results in open literature. Specifically, the topology sections designed include antenna input matching, transmit/receive switch, necessary filters, low noise amplifier, mixer and phase lock loop units. The numerical TM, (designed) circuit parameters are duly addressed in appropriate ADS simulation tools and performance evaluations are conducted. Observed results including any deviations are identified and reported. The thesis concludes with a summary and indicates direction for future work.
Show less - Date Issued
- 2007
- PURL
- http://purl.flvc.org/fau/fd/FA00012559
- Subject Headings
- Integrated circuits--Very large scale integration--Design and construction, Metal oxide semiconductors, Complementary, Bluetooth technology, Network performance (Telecommunication)
- Format
- Document (PDF)
- Title
- A VLSI implementable learning algorithm.
- Creator
- Ruiz, Laura V., Florida Atlantic University, Pandya, Abhijit S., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
- Abstract/Description
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A top-down design methodology using hardware description languages (HDL's) and powerful design, analysis, synthesis and layout software tools for electronic circuit design is described and applied to the design of a single layer artificial neural network that incorporates on-chip learning. Using the perception learning algorithm, these simple neurons learn a classification problem in 10.55 microseconds in one application. The objective is to describe a methodology by following the design of a...
Show moreA top-down design methodology using hardware description languages (HDL's) and powerful design, analysis, synthesis and layout software tools for electronic circuit design is described and applied to the design of a single layer artificial neural network that incorporates on-chip learning. Using the perception learning algorithm, these simple neurons learn a classification problem in 10.55 microseconds in one application. The objective is to describe a methodology by following the design of a simple network. This methodology is later applied in the design of a novel architecture, a stochastic neural network. All issues related to algorithmic design for VLSI implementability are discussed and results of layout and timing analysis given over software simulations. A top-down design methodology is presented, including a brief introduction to HDL's and an overview of the software tools used throughout the design process. These tools make it possible now for a designer to complete a design in a relative short period of time. In-depth knowledge of computer architecture, VLSI fabrication, electronic circuits and integrated circuit design is not fundamental to accomplish a task that a few years ago would have required a large team of specialized experts in many fields. This may appeal to researchers from a wide background of knowledge, including computer scientists, mathematicians, and psychologists experimenting with learning algorithms. It is only in a hardware implementation of artificial neural network learning algorithms that the true parallel nature of these architectures could be fully tested. Most of the applications of neural networks are basically software simulations of the algorithms run on a single CPU executing sequential simulations of a parallel, richly interconnected architecture. This dissertation describes a methodology whereby a researcher experimenting with a known or new learning algorithm will be able to test it as it was intentionally designed for, on a parallel hardware architecture.
Show less - Date Issued
- 1996
- PURL
- http://purl.flvc.org/fcla/dt/12453
- Subject Headings
- Integrated circuits--Very large scale integration--Design and construction, Neural networks (Computer science)--Design and construction, Computer algorithms, Machine learning
- Format
- Document (PDF)
- Title
- A low power and high performance centralized full adder.
- Creator
- Srivastav, Sidharth., Florida Atlantic University, Pandya, Abhijit S., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
- Abstract/Description
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In this thesis, we proposed a low power and high performance architecture for 1-bit full adder design. The proposed architecture was proven to offer a wide range of performance ability in terms of power consumption and speed. We implemented the architecture using a 2-input 2 multiplexers, an XOR and an XNOR gate. The proposed architecture and the Standard full adder were designed and simulated using Lasi, Winspice and Silos. Silos, a logic simulation environment was used in the design and...
Show moreIn this thesis, we proposed a low power and high performance architecture for 1-bit full adder design. The proposed architecture was proven to offer a wide range of performance ability in terms of power consumption and speed. We implemented the architecture using a 2-input 2 multiplexers, an XOR and an XNOR gate. The proposed architecture and the Standard full adder were designed and simulated using Lasi, Winspice and Silos. Silos, a logic simulation environment was used in the design and verification of the proposed architecture and the standard full adder that were modeled with Verilog hardware description language. Lasi was used for the layout design of the proposed architecture and the standard full adder. After the layout, both the architectures were compiled separately using LASICKT and a corresponding .CIR file was generated. The .CIR file was imported and executed into WINSPICE3 for the simulation of the circuit.
Show less - Date Issued
- 2004
- PURL
- http://purl.flvc.org/fcla/dt/13188
- Subject Headings
- Digital integrated circuits, Metal oxide semiconductors, Complementary, Integrated circuits--Design and contruction, Verilog (Computer hardware description language), Mixed signal circuits--Design and construction--Computer-aided design
- Format
- Document (PDF)
- Title
- Transmitter-receiver system for time average fourier telescopy.
- Creator
- Pava, Diego F., Rhodes, William T., Florida Atlantic University, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
- Abstract/Description
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Time Average Fourier Telescopy (TAFT) has been proposed as a means for obtaining high-resolution, diffraction-limited images over large distances through ground-level horizontal-path atmospheric turbulence. Image data is collected in the spatial-frequency, or Fourier, domain by means of Fourier Telescopy; an inverse two dimensional Fourier transform yields the actual image. TAFT requires active illumination of the distant object by moving interference fringe patterns. Light reflected from the...
Show moreTime Average Fourier Telescopy (TAFT) has been proposed as a means for obtaining high-resolution, diffraction-limited images over large distances through ground-level horizontal-path atmospheric turbulence. Image data is collected in the spatial-frequency, or Fourier, domain by means of Fourier Telescopy; an inverse two dimensional Fourier transform yields the actual image. TAFT requires active illumination of the distant object by moving interference fringe patterns. Light reflected from the object is collected by a “light-bucket” detector, and the resulting electrical signal is digitized and subjected to a series of signal processing operations, including an all-critical averaging of the amplitude and phase of a number of narrow-band signals.
Show less - Date Issued
- 2014
- PURL
- http://purl.flvc.org/fau/fd/FA00004314
- Subject Headings
- Digital communications, Fourier analysis, Fourier integral operators, Interconnects (Integrated circuit technology), Radio -- Transmitter receivers -- Design and construction, Spread spectrum communications, Wireless sensor networks
- Format
- Document (PDF)
- Title
- Cache optimization for real-time embedded systems.
- Creator
- Asaduzzaman, Abu Sadath Mohammad, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
- Abstract/Description
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Cache memory is used, in most single-core and multi-core processors, to improve performance by bridging the speed gap between the main memory and CPU. Even though cache increases performance, it poses some serious challenges for embedded systems running real-time applications. Cache introduces execution time unpredictability due to its adaptive and dynamic nature and cache consumes vast amount of power to be operated. Energy requirement and execution time predictability are crucial for the...
Show moreCache memory is used, in most single-core and multi-core processors, to improve performance by bridging the speed gap between the main memory and CPU. Even though cache increases performance, it poses some serious challenges for embedded systems running real-time applications. Cache introduces execution time unpredictability due to its adaptive and dynamic nature and cache consumes vast amount of power to be operated. Energy requirement and execution time predictability are crucial for the success of real-time embedded systems. Various cache optimization schemes have been proposed to address the performance, power consumption, and predictability issues. However, currently available solutions are not adequate for real-time embedded systems as they do not address the performance, power consumption, and execution time predictability issues at the same time. Moreover, existing solutions are not suitable for dealing with multi-core architecture issues. In this dissertation, we develop a methodology through cache optimization for real-time embedded systems that can be used to analyze and improve execution time predictability and performance/power ratio at the same time. This methodology is effective for both single-core and multi-core systems. First, we develop a cache modeling and optimization technique for single-core systems to improve performance. Then, we develop a cache modeling and optimization technique for multi-core systems to improve performance/power ratio. We develop a cache locking scheme to improve execution time predictability for real-time systems. We introduce Miss Table (MT) based cache locking scheme with victim cache (VC) to improve predictability and performance/power ratio. MT holds information about memory blocks, which may cause more misses if not locked, to improve cache locking performance., VC temporarily stores the victim blocks from level-1 cache to improve cache hits. In addition, MT is used to improve cache replacement performance and VC is used to improve cache hits by supporting stream buffering. We also develop strategies to generate realistic workload by characterizing applications to simulate cache optimization and cache locking schemes. Popular MPEG4, H.264/AVC, FFT, MI, and DFT applications are used to run the simulation programs. Simulation results show that newly introduced Miss Table based cache locking scheme with victim cache significantly improves the predictability and performance/power ratio. In this work, a reduction of 33% in mean delay per task and a reduction of 41% in total power consumption are achieved by using MT and VCs while locking 25% of level-2 cache size in an 4-core system. It is also observed that execution time predictability can be improved by avoiding more than 50% cache misses while locking one-fourth of the cache size.
Show less - Date Issued
- 2009
- PURL
- http://purl.flvc.org/FAU/359919
- Subject Headings
- Real-time embedded systems and components, Embedded computer systems, Programming, Computer architecture, Integrated circuits, Design and construction, Signal processing, Digital techniques, Object-oriented methods (Computer science)
- Format
- Document (PDF)
- Title
- Configuration and assessment of hardware-in-the-loop-simulation with high resolution data to coordinate traffic signals.
- Creator
- Klanac, Ivica, Stevanovic, Aleksandar, Florida Atlantic University, College of Engineering and Computer Science, Department of Civil, Environmental and Geomatics Engineering
- Abstract/Description
-
Today, the information (signal timings, detector extension, phase sequence, etc.) to install traffic lights on the street are obtained from traffic software simulations platforms, meaning that information from simulation is not tested on the field (intersection where it will be installed) before the installation. Many installed controllers on the street use time of day (TOD) patterns due to cheaper cost than adaptive traffic control systems, but that is not the best solution for traffic...
Show moreToday, the information (signal timings, detector extension, phase sequence, etc.) to install traffic lights on the street are obtained from traffic software simulations platforms, meaning that information from simulation is not tested on the field (intersection where it will be installed) before the installation. Many installed controllers on the street use time of day (TOD) patterns due to cheaper cost than adaptive traffic control systems, but that is not the best solution for traffic volume changes that can occur during the day or even a month. To improve traffic signal operation most of the traffic signal controllers in the same corridor or zone operate in coordination mode. Furthermore, phases need to be in coordination to achieve “green wave”. Green wave is term used when in corridor traffic lights allow continues flow of traffic through intersections that are coordinated.
Show less - Date Issued
- 2016
- PURL
- http://purl.flvc.org/fau/fd/FA00004709, http://purl.flvc.org/fau/fd/FA00004709
- Subject Headings
- Digital control systems, Digital integrated circuits -- Design and construction, Hardware in the loop simulation, Highway engineering -- Safety measures, Traffic engineering -- Technological innovations, Traffic flow -- Management, Traffic signs and signals -- Control systems -- Methodology
- Format
- Document (PDF)