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Experimental modal analysis and dynamic response of PC boards with surface mount electronic components
Title
Experimental modal analysis and dynamic response of PC boards with surface mount electronic components.
Creator
Wang, Gang., Florida Atlantic University, Wong, Tin-Lup, College of Engineering and Computer Science, Department of Ocean and Mechanical Engineering
Abstract/Description
Experimental modal analysis was conducted on a FR-4 epoxy fiber glass electronic printed circuit board (PCB) and a same size PCB with surface mount component to determine the modal parameters of the first four flexural vibration modes. Structural dynamic modification (SDM) and finite element analysis (FEA) techniques were utilized to predict the dynamic behavior of the boards when surface mount assemblies were attached. Details of modal testing procedures and analytical modeling involved in...
Show moreExperimental modal analysis was conducted on a FR-4 epoxy fiber glass electronic printed circuit board (PCB) and a same size PCB with surface mount component to determine the modal parameters of the first four flexural vibration modes. Structural dynamic modification (SDM) and finite element analysis (FEA) techniques were utilized to predict the dynamic behavior of the boards when surface mount assemblies were attached. Details of modal testing procedures and analytical modeling involved in SDM and FEA were described. Processes of investigating suitable predicting model were presented. Results from the study indicate that the component can be modeled as a point mass under certain circumstance. But it is important to include the rotary inertia effects of the component in response prediction for the modes involving torsional vibration.
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Date Issued
1990
PURL
http://purl.flvc.org/fcla/dt/14671
Subject Headings
Printed circuits--Testing, Electronic packaging, Surface mount technology
Format
Document (PDF)
Survey of design techniques for signal integrity
Title
Survey of design techniques for signal integrity.
Creator
Karnati, Raghuveer., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description
Signal Integrity is a major bottleneck for DSM designs. Signal integrity refers to wide variety of problems, which leads to misconception. Signal integrity causes delay or noise at the high-level, but this boils down to resistance, capacitance and inductance (RLC) at circuit level. Several analysis and reduction techniques were proposed for reducing these effects on signal integrity. This work solves the misconception by encompassing different problems Chat effect signal integrity and can be...
Show moreSignal Integrity is a major bottleneck for DSM designs. Signal integrity refers to wide variety of problems, which leads to misconception. Signal integrity causes delay or noise at the high-level, but this boils down to resistance, capacitance and inductance (RLC) at circuit level. Several analysis and reduction techniques were proposed for reducing these effects on signal integrity. This work solves the misconception by encompassing different problems Chat effect signal integrity and can be good reference for a integrated circuit designer. The objective is to analyze these modeling methods, reduction techniques, tools and make recommendations that aids in developing a methodology for perfect design closure with an emphasis on signal integrity. These recommendations would form a basis for developing a methodology to analyze interference effects at higher levels of abstraction.
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Date Issued
2003
PURL
http://purl.flvc.org/fcla/dt/13065
Subject Headings
Integrated circuits--Design and construction, Signal processing, Electronic circuit design
Format
Document (PDF)
Effects of added components on the dynamic modeling of printed circuit boards
Title
Effects of added components on the dynamic modeling of printed circuit boards.
Creator
Vallamattam, Bijoy Kurian., Florida Atlantic University, Stevens, Karl K., College of Engineering and Computer Science, Department of Ocean and Mechanical Engineering
Abstract/Description
Dynamic modeling of Printed Circuit Boards (PCBs) with mounted components, was investigated via the example of a PC network card by removing components in different stages and examining the resulting effects on the modal properties. Modal test results were compared with those from an ANSYS finite element analysis. Questions considered were: a) Do added components have a significant effect on the modal properties of a PCB and what are the effects ? b) How much variation is there in natural...
Show moreDynamic modeling of Printed Circuit Boards (PCBs) with mounted components, was investigated via the example of a PC network card by removing components in different stages and examining the resulting effects on the modal properties. Modal test results were compared with those from an ANSYS finite element analysis. Questions considered were: a) Do added components have a significant effect on the modal properties of a PCB and what are the effects ? b) How much variation is there in natural frequencies from board to board and test to test for a single board? c) Can a board with attached components reasonably be modeled as a uniform elastic plate with an "equivalent" density and modulus of elasticity? Results obtained indicate that added components do have significant effects on the board modal properties, less so for the lower modes than for the higher modes. There was only slight variation in the natural frequencies from board to board and from test to test for a single board. For the first two modes of vibration, it was found that the board considered could be modeled as a uniform elastic plate with "equivalent" properties, provided an appropriate value of equivalent elastic modulus was used. General findings, applicable to any PCB design, are presented.
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Date Issued
1994
PURL
http://purl.flvc.org/fcla/dt/15015
Subject Headings
Modal analysis, Printed circuits--Mathematical models, Printed circuits--Design and construction--Data processing, Electronic systems
Format
Document (PDF)
Parallel architectures and algorithms for digital filter VLSI implementation
Title
Parallel architectures and algorithms for digital filter VLSI implementation.
Creator
Desai, Pratik Vishnubhai., Florida Atlantic University, Sudhakar, Raghavan
Abstract/Description
In many scientific and signal processing applications, there are increasing demands for large volume and high speed computations, which call for not only high-speed low power computing hardware, but also for novel approaches in developing new algorithms and architectures. This thesis is concerned with the development of such architectures and algorithms suitable for the VLSI implementation of recursive and nonrecursive 1-dimension digital filters using multiple slower processing elements. As...
Show moreIn many scientific and signal processing applications, there are increasing demands for large volume and high speed computations, which call for not only high-speed low power computing hardware, but also for novel approaches in developing new algorithms and architectures. This thesis is concerned with the development of such architectures and algorithms suitable for the VLSI implementation of recursive and nonrecursive 1-dimension digital filters using multiple slower processing elements. As the background for the development, vectorization techniques such as state-space modeling, block processing, and look ahead computation are introduced. Concurrent architectures such as systolic arrays, wavefront arrays and appropriate parallel filter realizations such as lattice, all-pass, and wave filters are reviewed. A fully hardware efficient systolic array architecture termed as Multiplexed Block-State Filter is proposed for the high speed implementation of lattice and direct realizations of digital filters. The thesis also proposes a new simplified algorithm, Alternate Pole Pairing Algorithm, for realizing an odd order recursive filter as the sum of two all-pass filters. Performance of the proposed schemes are verified through numerical examples and simulation results.
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Date Issued
1995
PURL
http://purl.flvc.org/fcla/dt/15155
Subject Headings
Integrated circuits--Very large scale integration, Parallel processing (Electronic computers), Computer network architectures, Algorithms (Data processing), Digital integrated circuits
Format
Document (PDF)
An empirical methodology for foundry specific submicroncmos analog circuit design
Title
An empirical methodology for foundry specific submicroncmos analog circuit design.
Creator
Rivas-Torres, Wilfredo, Roth, Zvi S., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description
Analog CMOS amplifiers are the building blocks for many analog circuit applications such as Operational Amplifiers, Comparators, Analog to Digital converters and others. This dissertation presents empirical design methodologies that are both intuitive and easy to follow on how to design these basic building blocks. The design method involves two main phases. In the first phase NMOS and PMOS transistor design kits, provided by a semiconductor foundry, are fully characterized using a set of...
Show moreAnalog CMOS amplifiers are the building blocks for many analog circuit applications such as Operational Amplifiers, Comparators, Analog to Digital converters and others. This dissertation presents empirical design methodologies that are both intuitive and easy to follow on how to design these basic building blocks. The design method involves two main phases. In the first phase NMOS and PMOS transistor design kits, provided by a semiconductor foundry, are fully characterized using a set of simulation experiments. In the second phase the user is capable of modifying all the relevant circuit design parameters while directly observing the tradeoffs in the circuit performance specifications. The final design is a circuit that very closely meets a set of desired design specifications for the design parameters selected. That second phase of the proposed design methodology utilizes a graphical user interface in which the designer moves a series of sliders allowing assessment of various design tradeoffs. The theoretical basis for this design methodology involves the transconductance efficiency and inversion coefficient parameters. In this dissertation there are no restrictive assumptions about the MOS transistor models. The design methodology can be used with any submicron model supported by the foundry process and in this sense the methods included within are general and non-dependent on any specific MOSFET model (e.g. EKV or BSIM3). As part of the design tradeoffs assessment process variations are included during the design process rather than as part of some post-nominal-design analysis. One of the central design parameters of each transistor in the circuit is the MOSFET inversion coefficient. The calculation of the inversion coefficient necessitates the determination of an important process parameter known as the Technology Current. In this dissertation a new method to determine the technology current is developed. Y Parameters are used to characterize the CMOS process and this also helps in improving the technology current determination method. A study of the properties of the technology current proves that indeed a single long channel saturated MOS transistor can be used to determine a fixed technology current value that is used in subsequent submicron CMOS design. Process corners and the variability of the technology current are also studied and the universality of the transconductance efficiency versus inversion coefficient response is shown to be true even in the presence of process variability.
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Date Issued
2013
PURL
http://purl.flvc.org/fau/fd/FA0004050
Subject Headings
Electron transport, Integrated circuits -- Design and construction, Metal oxide semiconductors, Complementary -- Mathematical models
Format
Document (PDF)
Developing a photovoltaic MPPT system
Title
Developing a photovoltaic MPPT system.
Creator
Bennett, Thomas, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description
Many issues related to the design and implementation of a maximum power point tracking (MPPT) converter as part of a photovoltaic (PV) system are addressed. To begin with, variations of the single diode model for a PV module are compared, to determine whether the simplest variation may be used for MPPT PV system modeling and analysis purposes. As part ot this determination, four different DC/DC converters are used in conjunction with these different PV models. This is to verify consistent...
Show moreMany issues related to the design and implementation of a maximum power point tracking (MPPT) converter as part of a photovoltaic (PV) system are addressed. To begin with, variations of the single diode model for a PV module are compared, to determine whether the simplest variation may be used for MPPT PV system modeling and analysis purposes. As part ot this determination, four different DC/DC converters are used in conjunction with these different PV models. This is to verify consistent behavior across the different PV models, as well as across the different converter topologies. Consistent results across the different PV models, will allow a simpler model to be used for simulation ana analysis. Consistent results with the different converters will verify that MPPT algorithms are converter independent. Next, MPPT algorithms are discussed. In particular,the differences between the perturb and observe, and the incremental conductance algorithms are explained and illustrated. A new MPPT algorithm is then proposed based on the deficiencies of the other algorithms. The proposed algorithm's parameters are optimized, and the results for different PV modules obtained. Realistic system losses are then considered, and their effect on the PV system is analyzed ; especially in regards to the MPPT algorithm. Finally, a PV system is implemented and the theoretical results, as well as the behavior of the newly proposed MPPT algorithm, are verified.
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Date Issued
2012
PURL
http://purl.flvc.org/FAU/3356887
Subject Headings
Photovoltaic power systems, Design, Electronic circuits, Electric current converters, Power (Mechanics), Renewable energy sources
Format
Document (PDF)
Hybrid reliability analysis of surface mounted assemblies
Title
Hybrid reliability analysis of surface mounted assemblies.
Creator
Wang, Junshi., Florida Atlantic University, Wong, Tin-Lup, College of Engineering and Computer Science, Department of Ocean and Mechanical Engineering
Abstract/Description
Simulations of bending and twisting of surface mounted assemblies have been performed using the hybrid analytical/experimental analysis approaches, and the results are presented. Analytical analyses were combined with experimental load-deformation characteristics of the surface mounted assemblies to predict the maximum allowable loadings and deflections that surface mounted assemblies can withstand before incurring failures. Simulation results obtained were in close agreement with the real...
Show moreSimulations of bending and twisting of surface mounted assemblies have been performed using the hybrid analytical/experimental analysis approaches, and the results are presented. Analytical analyses were combined with experimental load-deformation characteristics of the surface mounted assemblies to predict the maximum allowable loadings and deflections that surface mounted assemblies can withstand before incurring failures. Simulation results obtained were in close agreement with the real loading situations.
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Date Issued
1990
PURL
http://purl.flvc.org/fcla/dt/14611
Subject Headings
Printed circuits--Design and construction, Electronic packaging, Surface mount technology
Format
Document (PDF)
combined FEM-fracture mechanics analysis approach for I.C. packages
Title
A combined FEM-fracture mechanics analysis approach for I.C. packages.
Creator
Renavikar, Ajit Anand., Florida Atlantic University, Stevens, Karl K., College of Engineering and Computer Science, Department of Ocean and Mechanical Engineering
Abstract/Description
A study of the stress distribution in and fracture behavior of the hermetic glass seal in a typical Integrated Circuit package is presented herein. Finite Element Analysis and Fracture Mechanics approaches were found effective for this investigation. A prescribed load or displacement applied at the tip of the lead protruding from the package causes high stresses at the lead-glass interface, which can lead to cracking and fracture of the seal. An approach for finding the value of the allowable...
Show moreA study of the stress distribution in and fracture behavior of the hermetic glass seal in a typical Integrated Circuit package is presented herein. Finite Element Analysis and Fracture Mechanics approaches were found effective for this investigation. A prescribed load or displacement applied at the tip of the lead protruding from the package causes high stresses at the lead-glass interface, which can lead to cracking and fracture of the seal. An approach for finding the value of the allowable load or displacement applicable at the lead tip is discussed. A correlation with a standard crack shape is presented for the 3-D model of the package. An extension of the problem revealing the effects of crack propagation on the stress intensity factor for the glass material is presented in later chapters. The J-integral method from Fracture Mechanics is found to be extremely useful for this investigation. A decline in the stress intensity factor with crack growth was observed from this study.
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Date Issued
1989
PURL
http://purl.flvc.org/fcla/dt/14511
Subject Headings
Integrated circuits--Fracture, Fracture mechanics, Finite element method, Electronics--Materials--Fatigue
Format
Document (PDF)
Design ofMOSFET ultra-wideband low noise amplifiers
Title
Design ofMOSFET ultra-wideband low noise amplifiers.
Creator
Camacho, Esteban, Bagby, Jonathan S., Florida Atlantic University
Abstract/Description
Ultra-Wide band (UWB) systems are a new wireless technology capable of transmitting data over a wide spectrum of frequency bands with very low power and high data rates. This technology has the potential to replace almost every cable at home or in an office with a wireless connection. In a UWB receiver, a radio frequency (RF) low noise amplifier (LNA) is one of the most important components. This thesis discusses the entire process involving the design ofUWB low noise amplifiers including a...
Show moreUltra-Wide band (UWB) systems are a new wireless technology capable of transmitting data over a wide spectrum of frequency bands with very low power and high data rates. This technology has the potential to replace almost every cable at home or in an office with a wireless connection. In a UWB receiver, a radio frequency (RF) low noise amplifier (LNA) is one of the most important components. This thesis discusses the entire process involving the design ofUWB low noise amplifiers including a detailed stage by stage analysis of a computer aided design (CAD) of a MOSFET UWB LNA. Simulation tools and concepts from Level I equations are used in order to design a circuit with a realistic MOS model such as the BSIM3 used in this work. The LNA shows improved power consumption over the designs it is based on while still producing comparable results.
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Date Issued
2008
PURL
http://purl.flvc.org/fau/fd/FA00012510
Subject Headings
Electronic circuit design, Integrated circuits--Very large scale integration, Metal-oxide semiconductor field-effect transistors--Design, Power transistors--Design
Format
Document (PDF)
Analysis of a novel class of fault-tolerant multistage interconnection networks
Title
Analysis of a novel class of fault-tolerant multistage interconnection networks.
Creator
Huang, Chien-Jen, Florida Atlantic University, Mahgoub, Imad, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description
Multistage interconnection networks (MINs) have become an important subset of the interconnection networks which are used to communicate between processors and memory modules for large scale multiprocessor systems. Unfortunately, unique path MINs lack fault tolerance. In this dissertation, a novel scheme for constructing fault-tolerant MINs is presented. We first partition the given MINs into even sized partitions and show some fault-tolerant properties of the partitioned MINs. Using three...
Show moreMultistage interconnection networks (MINs) have become an important subset of the interconnection networks which are used to communicate between processors and memory modules for large scale multiprocessor systems. Unfortunately, unique path MINs lack fault tolerance. In this dissertation, a novel scheme for constructing fault-tolerant MINs is presented. We first partition the given MINs into even sized partitions and show some fault-tolerant properties of the partitioned MINs. Using three stages of multiplexers/demultiplexers, an augmenting scheme which takes advantage of locality in program execution is then proposed to further improve the fault-tolerant ability and performance of the partitioned MINs. The topological characteristics of augmented partitioned multistage interconnection networks (APMINs) are analyzed. Based on switch fault model, simulations have been carried out to evaluate the full access and dynamic full access capabilities of APMINs. The results show that the proposed scheme significantly improves the fault-tolerant capability of MINs. Cost effectiveness of this new scheme in terms of cost, full access, dynamic full access, locality, and average path length has also been evaluated. It has been shown that this new scheme is more cost effective for high switch failure rate and/or large size networks. Analytical modeling techniques have been developed to evaluate the performance of AP-Omega network and AP-Omega network-based multiprocessor systems. The performance of Omega, modified Omega, and AP-Omega networks in terms of processor utilization and processor waiting time have been compared and the results show that the new scheme indeed, improves the performance both in network level and in system level. Finally, based on the reliability of serial/parallel network components, models for evaluating the terminal reliability and the network reliability of AP-Omega network using upper and lower bound measures have also been proposed and the results show that applying locality improve APMINs' reliability.
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Date Issued
1993
PURL
http://purl.flvc.org/fcla/dt/12345
Subject Headings
Integratged circuits--Very large scale integration, Fault-tolerant computing, Computer architecture, Parallel processing (Electronic computers)
Format
Document (PDF)
DCVS logic synthesis
Title
DCVS logic synthesis.
Creator
Xiao, Kang., Florida Atlantic University, Barrett, Raymond L. Jr., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description
Implementation of CMOS combinational logic with Differential Cascode Voltage Switch logic (DCVS) may have many advantages over the traditional CMOS logic approaches with respect to device count, layout density and timing. DCVS is an ideal target technology for a logic synthesis system in that it provides a complete function cover by providing the function and its complement simultaneously. DCVS is also more testable due to this. We have developed for IBM's DCVS technology a synthesis...
Show moreImplementation of CMOS combinational logic with Differential Cascode Voltage Switch logic (DCVS) may have many advantages over the traditional CMOS logic approaches with respect to device count, layout density and timing. DCVS is an ideal target technology for a logic synthesis system in that it provides a complete function cover by providing the function and its complement simultaneously. DCVS is also more testable due to this. We have developed for IBM's DCVS technology a synthesis algorithm and a new test generation approach, that are based on topologies rather than individual logic functions. We have found that 19 and 363 DCVS topologies can represent 256 and 65,536 functions, respectively, for the 3- and 4-varaible cases. Physical defect analysis was conducted with the aid of a building block approach to analyze the n-type logic tree and provides a basis for evolving hierarchical test pattern generation for the topologies.
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Date Issued
1992
PURL
http://purl.flvc.org/fcla/dt/14850
Subject Headings
Integrated circuits--Very large scale integration--Data processing, Metal oxide semiconductors, Complementary, Computer-aided design, Electronic systems, Logic design--Data processing
Format
Document (PDF)