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Title: Novel multiplexer-based architectures for full adder design.
Creator: Al-Sheraidah, Abdulkarim K., Florida Atlantic University, Wang, Yuke
Abstract/Description: We propose five new Multiplexer-Based architectures for 1-bit full adder design. Using a 2-transistors multiplexer gate to implement the first architecture, we are able to produce a 12-transistor full adder cell, Comparing it to four different 10-transistors low-power full adder cells reported previously in literature, the new adder cell named MBA1-12T out performs all of them in power consumption and speed. By implementing those architectures using the 2-input CMOS multiplexer with pass...
Show moreWe propose five new Multiplexer-Based architectures for 1-bit full adder design. Using a 2-transistors multiplexer gate to implement the first architecture, we are able to produce a 12-transistor full adder cell, Comparing it to four different 10-transistors low-power full adder cells reported previously in literature, the new adder cell named MBA1-12T out performs all of them in power consumption and speed. By implementing those architectures using the 2-input CMOS multiplexer with pass-gates, five new high-performance full adder cells are obtained. Those new adder cells are tested along with the conventional 28-transistor CMOS adder cell. Testing results shows that the new adder cells have higher speed and lower power delay product values than the conventional 28-transistor CMOS adder cell.
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Date Issued: 2000
PURL: http://purl.flvc.org/fcla/dt/12667
Subject Headings: Metal oxide semiconductors, Complementary, Digital integrated circuits
Format: Document (PDF)

Title: Design of 10-transistor low-power full adders.
Creator: Bui, Hung Tien., Florida Atlantic University, Wang, Yuke
Abstract/Description: We propose two approaches to design 1-bit full adders which can yield good performance at low power consumption. In the first approach, we design XOR/XNOR gates using a minimal number of CMOS transistors. Comparing with 10 different XOR/XNOR gates reported in literature, the new XOR/XNOR gates consume less power. The gates consisting of the smallest number of transistors are combined to create 1-bit full adders. The process is systematic and yields a total of 42 10-transistor full adders, 41...
Show moreWe propose two approaches to design 1-bit full adders which can yield good performance at low power consumption. In the first approach, we design XOR/XNOR gates using a minimal number of CMOS transistors. Comparing with 10 different XOR/XNOR gates reported in literature, the new XOR/XNOR gates consume less power. The gates consisting of the smallest number of transistors are combined to create 1-bit full adders. The process is systematic and yields a total of 42 10-transistor full adders, 41 of which are new. Simulation results show that most of the new adders perform better than a previously existing 10-transistor adder and a complementary CMOS adder in terms of power and speed with heavier load. Three adders consistently perform better. In the second approach, we utilized a method called the centralized design to create four new 10-transistor full adders. Simulation results show that these new adders perform better than the previously existing 10-transistor and the complementary CMOS adder.
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Date Issued: 2000
PURL: http://purl.flvc.org/fcla/dt/15759
Subject Headings: Digital integrated circuits, Low voltage integrated circuits, Metal oxide semiconductors, Complementary
Format: Document (PDF)

Title: Low-level and high-level correlation for image registration.
Creator: Mandalia, Anil Dhirajlal., Florida Atlantic University, Sudhakar, Raghavan, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: The fundamental goal of a machine vision system in the inspection of an assembled printed circuit board is to locate the integrated circuit(IC) components. These components are then checked for their position and orientation with respect to a given position and orientation of the model and to detect deviations. To this end, a method based on a modified two-level correlation scheme is presented in this thesis. In the first level, Low-Level correlation, a modified two-stage template matching...
Show moreThe fundamental goal of a machine vision system in the inspection of an assembled printed circuit board is to locate the integrated circuit(IC) components. These components are then checked for their position and orientation with respect to a given position and orientation of the model and to detect deviations. To this end, a method based on a modified two-level correlation scheme is presented in this thesis. In the first level, Low-Level correlation, a modified two-stage template matching method is proposed. It makes use of the random search techniques, better known as the Monte Carlo method, to speed up the matching process on binarized version of the images. Due to the random search techniques, there is uncertainty involved in the location where the matches are found. In the second level, High-Level correlation, an evidence scheme based on the Dempster-Shafer formalism is presented to resolve the uncertainty. Experiment results performed on a printed circuit board containing mounted integrated components is also presented to demonstrate the validity of the techniques.
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Date Issued: 1990
PURL: http://purl.flvc.org/fcla/dt/14635
Subject Headings: Image processing--Digital techniques, Computer vision, Integrated circuits
Format: Document (PDF)

Title: Parallel architectures and algorithms for digital filter VLSI implementation.
Creator: Desai, Pratik Vishnubhai., Florida Atlantic University, Sudhakar, Raghavan
Abstract/Description: In many scientific and signal processing applications, there are increasing demands for large volume and high speed computations, which call for not only high-speed low power computing hardware, but also for novel approaches in developing new algorithms and architectures. This thesis is concerned with the development of such architectures and algorithms suitable for the VLSI implementation of recursive and nonrecursive 1-dimension digital filters using multiple slower processing elements. As...
Show moreIn many scientific and signal processing applications, there are increasing demands for large volume and high speed computations, which call for not only high-speed low power computing hardware, but also for novel approaches in developing new algorithms and architectures. This thesis is concerned with the development of such architectures and algorithms suitable for the VLSI implementation of recursive and nonrecursive 1-dimension digital filters using multiple slower processing elements. As the background for the development, vectorization techniques such as state-space modeling, block processing, and look ahead computation are introduced. Concurrent architectures such as systolic arrays, wavefront arrays and appropriate parallel filter realizations such as lattice, all-pass, and wave filters are reviewed. A fully hardware efficient systolic array architecture termed as Multiplexed Block-State Filter is proposed for the high speed implementation of lattice and direct realizations of digital filters. The thesis also proposes a new simplified algorithm, Alternate Pole Pairing Algorithm, for realizing an odd order recursive filter as the sum of two all-pass filters. Performance of the proposed schemes are verified through numerical examples and simulation results.
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Date Issued: 1995
PURL: http://purl.flvc.org/fcla/dt/15155
Subject Headings: Integrated circuits--Very large scale integration, Parallel processing (Electronic computers), Computer network architectures, Algorithms (Data processing), Digital integrated circuits
Format: Document (PDF)

Title: A novel DSP scheme for image compression and HDTV transmission.
Creator: Dong, Xu., Florida Atlantic University, Sudhakar, Raghavan, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: The main objective of the research is to develop computationally efficient hybrid coding schemes for the low bit implementations of image frames and image sequences. The basic fractal block coding can compress a relatively low resolution image efficiently without blocky artifacts, but it does not converge well at the high frequency edges. This research proposes a hybrid multi-resolution scheme which combines the advantages of fractal and DCT coding schemes. The fractal coding is applied to...
Show moreThe main objective of the research is to develop computationally efficient hybrid coding schemes for the low bit implementations of image frames and image sequences. The basic fractal block coding can compress a relatively low resolution image efficiently without blocky artifacts, but it does not converge well at the high frequency edges. This research proposes a hybrid multi-resolution scheme which combines the advantages of fractal and DCT coding schemes. The fractal coding is applied to get a lower resolution, quarter size output image and DCT is then used to encode the error residual between original full bandwidth image signal and the fractal decoded image signal. At the decoder side, the full resolution, full size reproduced image is generated by adding decoded error image to the decoded fractal image. Also, the lower resolution, quarter size output image is automatically given by the iteration function scheme without having to spend extra effort. Other advantages of the scheme are that the high resolution layer is generated by error image which covers the bandwidth loss of the lower resolution layer as well as the coding error of the lower resolution layer, and that it does not need a sophisticated classification procedure. A series of computer simulation experiments are conducted and their results are presented to illustrate the merit of the scheme. The hybrid fractal coding method is then extended to process motion sequences as well. A new scheme is proposed for motion vector detection and motion compensation, by judiciously combining the techniques of fractal compression and block matching. The advantage of this scheme is that it improves the performance of the motion compensation, while keeping the overall computational complexity low for each frame. The simulation results on realistic video conference image sequences support the superiority of the proposed method in terms of reproduced picture quality and compression ratio.
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Date Issued: 1995
PURL: http://purl.flvc.org/fcla/dt/12407
Subject Headings: Hybrid integrated circuits, Image compression, Fractals, Image processing--Digital techniques, High definition television
Format: Document (PDF)

Title: System level simulations of an optical character recognition system.
Creator: Phadnis, Mangirish Jayawant., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Optical Character Recognition systems have many applications in today's world of electronic computing. Various software implementations are currently being used. This thesis evolves a massively parallel hardware implementation for the system that is VLSI scaleable and may lead to substantial increase in the processing speed. This system involves various stages for preprocessing and processing of the image implemented with SIMD architecture, using simple processing elements and near neighbor...
Show moreOptical Character Recognition systems have many applications in today's world of electronic computing. Various software implementations are currently being used. This thesis evolves a massively parallel hardware implementation for the system that is VLSI scaleable and may lead to substantial increase in the processing speed. This system involves various stages for preprocessing and processing of the image implemented with SIMD architecture, using simple processing elements and near neighbor communications. The architecture evolved is simulated using the Verilog Hardware Description Language. This project should provide a framework for a massively parallel processing architecture for such systems. It is expected that this project will lead to the design and implementation of a real time system.
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Date Issued: 1994
PURL: http://purl.flvc.org/fcla/dt/15106
Subject Headings: Optical character recognition devices, Integrated circuits--Very large scale integration, Optical scanners, Image processing--Digital techniques
Format: Document (PDF)

Title: A low power and high performance centralized full adder.
Creator: Srivastav, Sidharth., Florida Atlantic University, Pandya, Abhijit S., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: In this thesis, we proposed a low power and high performance architecture for 1-bit full adder design. The proposed architecture was proven to offer a wide range of performance ability in terms of power consumption and speed. We implemented the architecture using a 2-input 2 multiplexers, an XOR and an XNOR gate. The proposed architecture and the Standard full adder were designed and simulated using Lasi, Winspice and Silos. Silos, a logic simulation environment was used in the design and...
Show moreIn this thesis, we proposed a low power and high performance architecture for 1-bit full adder design. The proposed architecture was proven to offer a wide range of performance ability in terms of power consumption and speed. We implemented the architecture using a 2-input 2 multiplexers, an XOR and an XNOR gate. The proposed architecture and the Standard full adder were designed and simulated using Lasi, Winspice and Silos. Silos, a logic simulation environment was used in the design and verification of the proposed architecture and the standard full adder that were modeled with Verilog hardware description language. Lasi was used for the layout design of the proposed architecture and the standard full adder. After the layout, both the architectures were compiled separately using LASICKT and a corresponding .CIR file was generated. The .CIR file was imported and executed into WINSPICE3 for the simulation of the circuit.
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Date Issued: 2004
PURL: http://purl.flvc.org/fcla/dt/13188
Subject Headings: Digital integrated circuits, Metal oxide semiconductors, Complementary, Integrated circuits--Design and contruction, Verilog (Computer hardware description language), Mixed signal circuits--Design and construction--Computer-aided design
Format: Document (PDF)

Title: Transmitter-receiver system for time average fourier telescopy.
Creator: Pava, Diego F., Rhodes, William T., Florida Atlantic University, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Time Average Fourier Telescopy (TAFT) has been proposed as a means for obtaining high-resolution, diffraction-limited images over large distances through ground-level horizontal-path atmospheric turbulence. Image data is collected in the spatial-frequency, or Fourier, domain by means of Fourier Telescopy; an inverse two dimensional Fourier transform yields the actual image. TAFT requires active illumination of the distant object by moving interference fringe patterns. Light reflected from the...
Show moreTime Average Fourier Telescopy (TAFT) has been proposed as a means for obtaining high-resolution, diffraction-limited images over large distances through ground-level horizontal-path atmospheric turbulence. Image data is collected in the spatial-frequency, or Fourier, domain by means of Fourier Telescopy; an inverse two dimensional Fourier transform yields the actual image. TAFT requires active illumination of the distant object by moving interference fringe patterns. Light reflected from the object is collected by a “light-bucket” detector, and the resulting electrical signal is digitized and subjected to a series of signal processing operations, including an all-critical averaging of the amplitude and phase of a number of narrow-band signals.
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Date Issued: 2014
PURL: http://purl.flvc.org/fau/fd/FA00004314
Subject Headings: Digital communications, Fourier analysis, Fourier integral operators, Interconnects (Integrated circuit technology), Radio -- Transmitter receivers -- Design and construction, Spread spectrum communications, Wireless sensor networks
Format: Document (PDF)

Title: Cache optimization for real-time embedded systems.
Creator: Asaduzzaman, Abu Sadath Mohammad, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Cache memory is used, in most single-core and multi-core processors, to improve performance by bridging the speed gap between the main memory and CPU. Even though cache increases performance, it poses some serious challenges for embedded systems running real-time applications. Cache introduces execution time unpredictability due to its adaptive and dynamic nature and cache consumes vast amount of power to be operated. Energy requirement and execution time predictability are crucial for the...
Show moreCache memory is used, in most single-core and multi-core processors, to improve performance by bridging the speed gap between the main memory and CPU. Even though cache increases performance, it poses some serious challenges for embedded systems running real-time applications. Cache introduces execution time unpredictability due to its adaptive and dynamic nature and cache consumes vast amount of power to be operated. Energy requirement and execution time predictability are crucial for the success of real-time embedded systems. Various cache optimization schemes have been proposed to address the performance, power consumption, and predictability issues. However, currently available solutions are not adequate for real-time embedded systems as they do not address the performance, power consumption, and execution time predictability issues at the same time. Moreover, existing solutions are not suitable for dealing with multi-core architecture issues. In this dissertation, we develop a methodology through cache optimization for real-time embedded systems that can be used to analyze and improve execution time predictability and performance/power ratio at the same time. This methodology is effective for both single-core and multi-core systems. First, we develop a cache modeling and optimization technique for single-core systems to improve performance. Then, we develop a cache modeling and optimization technique for multi-core systems to improve performance/power ratio. We develop a cache locking scheme to improve execution time predictability for real-time systems. We introduce Miss Table (MT) based cache locking scheme with victim cache (VC) to improve predictability and performance/power ratio. MT holds information about memory blocks, which may cause more misses if not locked, to improve cache locking performance., VC temporarily stores the victim blocks from level-1 cache to improve cache hits. In addition, MT is used to improve cache replacement performance and VC is used to improve cache hits by supporting stream buffering. We also develop strategies to generate realistic workload by characterizing applications to simulate cache optimization and cache locking schemes. Popular MPEG4, H.264/AVC, FFT, MI, and DFT applications are used to run the simulation programs. Simulation results show that newly introduced Miss Table based cache locking scheme with victim cache significantly improves the predictability and performance/power ratio. In this work, a reduction of 33% in mean delay per task and a reduction of 41% in total power consumption are achieved by using MT and VCs while locking 25% of level-2 cache size in an 4-core system. It is also observed that execution time predictability can be improved by avoiding more than 50% cache misses while locking one-fourth of the cache size.
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Date Issued: 2009
PURL: http://purl.flvc.org/FAU/359919
Subject Headings: Real-time embedded systems and components, Embedded computer systems, Programming, Computer architecture, Integrated circuits, Design and construction, Signal processing, Digital techniques, Object-oriented methods (Computer science)
Format: Document (PDF)

Title: Configuration and assessment of hardware-in-the-loop-simulation with high resolution data to coordinate traffic signals.
Creator: Klanac, Ivica, Stevanovic, Aleksandar, Florida Atlantic University, College of Engineering and Computer Science, Department of Civil, Environmental and Geomatics Engineering
Abstract/Description: Today, the information (signal timings, detector extension, phase sequence, etc.) to install traffic lights on the street are obtained from traffic software simulations platforms, meaning that information from simulation is not tested on the field (intersection where it will be installed) before the installation. Many installed controllers on the street use time of day (TOD) patterns due to cheaper cost than adaptive traffic control systems, but that is not the best solution for traffic...
Show moreToday, the information (signal timings, detector extension, phase sequence, etc.) to install traffic lights on the street are obtained from traffic software simulations platforms, meaning that information from simulation is not tested on the field (intersection where it will be installed) before the installation. Many installed controllers on the street use time of day (TOD) patterns due to cheaper cost than adaptive traffic control systems, but that is not the best solution for traffic volume changes that can occur during the day or even a month. To improve traffic signal operation most of the traffic signal controllers in the same corridor or zone operate in coordination mode. Furthermore, phases need to be in coordination to achieve “green wave”. Green wave is term used when in corridor traffic lights allow continues flow of traffic through intersections that are coordinated.
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Date Issued: 2016
PURL: http://purl.flvc.org/fau/fd/FA00004709, http://purl.flvc.org/fau/fd/FA00004709
Subject Headings: Digital control systems, Digital integrated circuits -- Design and construction, Hardware in the loop simulation, Highway engineering -- Safety measures, Traffic engineering -- Technological innovations, Traffic flow -- Management, Traffic signs and signals -- Control systems -- Methodology
Format: Document (PDF)

Digital integrated circuits (4)	+ -
Image processing--Digital techniques (3)	+ -
Metal oxide semiconductors, Complementary (3)	+ -
Integrated circuits (2)	+ -
Integrated circuits--Very large scale integration (2)	+ -

Algorithms (Data processing) (1)	+ -
Computer architecture (1)	+ -
Computer network architectures (1)	+ -
Computer vision (1)	+ -
Design and construction (1)	+ -
Digital communications (1)	+ -
Digital control systems (1)	+ -
Digital integrated circuits -- Design and construction (1)	+ -
Digital techniques (1)	+ -
Embedded computer systems (1)	+ -
Fourier analysis (1)	+ -
Fourier integral operators (1)	+ -
Fractals (1)	+ -
Hardware in the loop simulation (1)	+ -
High definition television (1)	+ -
Highway engineering -- Safety measures (1)	+ -
Hybrid integrated circuits (1)	+ -
Image compression (1)	+ -
Integrated circuits--Design and contruction (1)	+ -
Interconnects (Integrated circuit technology) (1)	+ -
Low voltage integrated circuits (1)	+ -
Mixed signal circuits--Design and construction--Computer-aided design (1)	+ -
Object-oriented methods (Computer science) (1)	+ -
Optical character recognition devices (1)	+ -
Optical scanners (1)	+ -

Florida Atlantic University (9)	+ -
College of Engineering and Computer Science (7)	+ -
Department of Computer and Electrical Engineering and Computer Science (6)	+ -
Sudhakar, Raghavan (3)	+ -
Wang, Yuke (2)	+ -

Al-Sheraidah, Abdulkarim K. (1)	+ -
Asaduzzaman, Abu Sadath Mohammad (1)	+ -
Bui, Hung Tien. (1)	+ -
Department of Civil, Environmental and Geomatics Engineering (1)	+ -
Desai, Pratik Vishnubhai. (1)	+ -
Dong, Xu. (1)	+ -
Klanac, Ivica (1)	+ -
Mandalia, Anil Dhirajlal. (1)	+ -
Pandya, Abhijit S. (1)	+ -
Pava, Diego F. (1)	+ -
Phadnis, Mangirish Jayawant. (1)	+ -
Rhodes, William T. (1)	+ -
Shankar, Ravi (1)	+ -
Srivastav, Sidharth. (1)	+ -
Stevanovic, Aleksandar (1)	+ -

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