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Alopex for handwritten digit recognition: Algorithmic verifications
Title
Alopex for handwritten digit recognition: Algorithmic verifications.
Creator
Martin, Gregory A., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description
Alopex is a biologically influenced computation paradigm that uses a stochastic procedure to find the global optimum of linear and nonlinear functions. It maps to a hierarchical SIMD (Single-Instruction-Multiple-Data) architecture with simple neuronal processing elements (PE's), therefore the large amount of interconnects in other types of neural networks are not required and more efficient utilization of chip level and board level "real estate" is realized. In this study, verifications were...
Show moreAlopex is a biologically influenced computation paradigm that uses a stochastic procedure to find the global optimum of linear and nonlinear functions. It maps to a hierarchical SIMD (Single-Instruction-Multiple-Data) architecture with simple neuronal processing elements (PE's), therefore the large amount of interconnects in other types of neural networks are not required and more efficient utilization of chip level and board level "real estate" is realized. In this study, verifications were performed on the use of a simplified Alopex algorithm in handwritten digit recognition with the intent that the verified algorithm be digitally implementable. The inputs to the simulated Alopex hardware are a set of 32 features extracted from the input characters. Although the goal of verifying the algorithm was not achieved, a firm direction for future studies has been established and a flexible software model for these future studies is available.
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Date Issued
1992
PURL
http://purl.flvc.org/fcla/dt/14842
Subject Headings
Algorithms--Data processing, Stochastic processes
Format
Document (PDF)
Radar cross section of an open-ended rectangular waveguide cavity: A massively parallel implementation applied to high-resolution radar cross section imaging
Title
Radar cross section of an open-ended rectangular waveguide cavity: A massively parallel implementation applied to high-resolution radar cross section imaging.
Creator
Vann, Laura Dominick., Florida Atlantic University, Helmken, Henry, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description
This thesis is concerned with adapting a sequential code that calculates the Radar Cross Section (RCS) of an open-ended rectangular waveguide cavity to a massively parallel computational platform. The primary motivation for doing this is to obtain wideband data over a large range of incident angles in order to generate a two-dimensional radar cross section image. Images generated from measured and computed data will be compared to evaluate program performance. The computer used in this...
Show moreThis thesis is concerned with adapting a sequential code that calculates the Radar Cross Section (RCS) of an open-ended rectangular waveguide cavity to a massively parallel computational platform. The primary motivation for doing this is to obtain wideband data over a large range of incident angles in order to generate a two-dimensional radar cross section image. Images generated from measured and computed data will be compared to evaluate program performance. The computer used in this implementation is a MasPar MP-1 single instruction, multiple data massively parallel computer consisting of 4,096 processors arranged in a two-dimensional mesh. The algorithm uses the mode matching method of analysis to match fields over the cavity aperture to obtain an expression for the scattered far field.
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Date Issued
1993
PURL
http://purl.flvc.org/fcla/dt/14984
Subject Headings
Radar cross sections, Algorithms--Data processing, Imaging systems
Format
Document (PDF)
Parallel architectures and algorithms for digital filter VLSI implementation
Title
Parallel architectures and algorithms for digital filter VLSI implementation.
Creator
Desai, Pratik Vishnubhai., Florida Atlantic University, Sudhakar, Raghavan
Abstract/Description
In many scientific and signal processing applications, there are increasing demands for large volume and high speed computations, which call for not only high-speed low power computing hardware, but also for novel approaches in developing new algorithms and architectures. This thesis is concerned with the development of such architectures and algorithms suitable for the VLSI implementation of recursive and nonrecursive 1-dimension digital filters using multiple slower processing elements. As...
Show moreIn many scientific and signal processing applications, there are increasing demands for large volume and high speed computations, which call for not only high-speed low power computing hardware, but also for novel approaches in developing new algorithms and architectures. This thesis is concerned with the development of such architectures and algorithms suitable for the VLSI implementation of recursive and nonrecursive 1-dimension digital filters using multiple slower processing elements. As the background for the development, vectorization techniques such as state-space modeling, block processing, and look ahead computation are introduced. Concurrent architectures such as systolic arrays, wavefront arrays and appropriate parallel filter realizations such as lattice, all-pass, and wave filters are reviewed. A fully hardware efficient systolic array architecture termed as Multiplexed Block-State Filter is proposed for the high speed implementation of lattice and direct realizations of digital filters. The thesis also proposes a new simplified algorithm, Alternate Pole Pairing Algorithm, for realizing an odd order recursive filter as the sum of two all-pass filters. Performance of the proposed schemes are verified through numerical examples and simulation results.
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Date Issued
1995
PURL
http://purl.flvc.org/fcla/dt/15155
Subject Headings
Integrated circuits--Very large scale integration, Parallel processing (Electronic computers), Computer network architectures, Algorithms (Data processing), Digital integrated circuits
Format
Document (PDF)