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COMPARATIVE EVALUATION OF SERVICE DISCIPLINES IN A TOKEN RING LOCAL AREA NETWORK: A SIMULATION STUDY
Title
A COMPARATIVE EVALUATION OF SERVICE DISCIPLINES IN A TOKEN RING LOCAL AREA NETWORK: A SIMULATION STUDY.
Creator
Syed, Majid Ali, Florida Atlantic University, Ilyas, Mohammad, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description
The primary emphasis of this thesis is to evaluate in comparative terms the performance of three types of service disciplines in a Token Ring Local Area Network. The service disciplines studied are exhaustive, gated and limited service. These service disciplines play an important role in the network performance, especially when some users are relatively less active than others in contributing traffic load to the network. Network performance for these service disciplines are compared to...
Show moreThe primary emphasis of this thesis is to evaluate in comparative terms the performance of three types of service disciplines in a Token Ring Local Area Network. The service disciplines studied are exhaustive, gated and limited service. These service disciplines play an important role in the network performance, especially when some users are relatively less active than others in contributing traffic load to the network. Network performance for these service disciplines are compared to determine which one of them gives better performance. Simulation is used for this study and results are presented in terms of average delay, queue lengths and delay histograms versus traffic intensity.
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Date Issued
1987
PURL
http://purl.flvc.org/fcla/dt/14388
Subject Headings
Local area networks (Computer networks)
Format
Document (PDF)
high-speed switching node architecture for ATM networks
Title
A high-speed switching node architecture for ATM networks.
Creator
Syed, Majid Ali, Florida Atlantic University, Ilyas, Mohammad, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description
This research is aimed towards the concept of a new switching node architecture for cell-switched Asynchronous Transfer Mode (ATM) networks. The proposed architecture has several distinguishing features when compared with existing Banyan based switching node. It has a cylindrical structure as opposed to a flat structure as found in Banyans. The wrap around property results in better link utilization as compared with existing Banyans beside resulting in reduced average route length. Simplified...
Show moreThis research is aimed towards the concept of a new switching node architecture for cell-switched Asynchronous Transfer Mode (ATM) networks. The proposed architecture has several distinguishing features when compared with existing Banyan based switching node. It has a cylindrical structure as opposed to a flat structure as found in Banyans. The wrap around property results in better link utilization as compared with existing Banyans beside resulting in reduced average route length. Simplified digit controlled routing is maintained as found in Banyans. The cylindrical nature of the architecture, results in pipeline activity. Such architecture tends to sort the traffic to a higher address, eliminating the need of a preprocessing node as a front end processing node. Approximate Markov chain analyses for the performance of the switching node with single input buffers is presented. The analyses are used to compute the time delay distribution of a cell leaving the node. A simulation tool is used to validate the analytical model. The simulation model is free from the critical assumptions which are necessary to develop the analytical model. It is shown that the analytical results closely match with the simulation results. This confirms the authenticity of the simulation model. We then study the performance of the switching node for various input buffer sizes. Low throughput with single input buffered switching node is observed; however, as the buffer size is increased from two to three the increase in throughput is more than 100%. No appreciable increase in node delay is noted when the buffer size is increased from two to three. We conclude that the optimum buffer size for large throughput is three and the maximum throughput with offered load of 0.9 and buffer size three is 0.75. This is because of head of line blocking phenomenon. A technique to overcome such inherent problem is presented. Several delays which a cell faces are analyzed and summarized below. The wait delay with buffer sizes one and two is high. However, the wait delay is negligible when the buffer size is increased beyond two. This is because increasing the buffer size reduces the head of line blocking. Thus more cells can move forward. Node delay and switched delay are comparable when the buffer size is greater than two. The delay offered is within a threshold range as noted for real time traffic. The delay is clock rate dependent and can be minimized by running the switching node at a higher clock speed. The worst delay noted for a switched cell for a node operating at a clock rate of 200 Mhz is 0.5 usec.
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Date Issued
1992
PURL
http://purl.flvc.org/fcla/dt/12309
Subject Headings
Computer networks, Computer architecture, Packet switching (Data transmission)
Format
Document (PDF)