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Title: New and Low-Cost Ways to Execute Biomedical Signal Processing.
Creator: Carvalho, Felipe, Shankar, Ravi
Abstract/Description: The human body is constantly sending, processing, and receiving information about its health. This internal communication process is often times achieved through tiny electrical signals, called Biomedical Signals (Biosignals). In this project, we investigate new ways to process Biosignals using embedded systems and computer simulations. We work with Texas Instruments’ OMAP L-138 Digital Signal Processor and Code Composer Studio IDE to process and analyze the electrical behavior of the human...
Show moreThe human body is constantly sending, processing, and receiving information about its health. This internal communication process is often times achieved through tiny electrical signals, called Biomedical Signals (Biosignals). In this project, we investigate new ways to process Biosignals using embedded systems and computer simulations. We work with Texas Instruments’ OMAP L-138 Digital Signal Processor and Code Composer Studio IDE to process and analyze the electrical behavior of the human heart (ECG Biosignals). In addition to creating computer codes to process such signals, one expected outcome of this research project is a series of tutorials exploring Biomedical concepts and digital signal processing algorithms. Our goal is to make Biomedical Signal Processing widely accessible, hence our decision to design around low-cost hardware and software, and to make all documentation available online at http://smartsystems.eng.fau.edu/biomedical-signal-processing/.
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Date Issued: 2014
PURL: http://purl.flvc.org/fau/fd/FA0005006
Subject Headings: College students --Research --United States.
Format: Document (PDF)

Title: Dynamically reconfigurable power-aware, highly scalable multiplier with reusable and locally optimized structures.
Creator: Shankar, Ravi, Florida Atlantic University
Date Issued: 2005-06
PURL: http://purl.flvc.org/fcla/dt/15796
Format: Document (PDF)

Title: Methods and aparatus for detecting the onset and relative degree of atherosclerosis in humans.
Creator: Shankar, Ravi, Florida Atlantic University
Date Issued: 1994-09
PURL: http://purl.flvc.org/fcla/dt/15849
Format: Document (PDF)

Title: Method for detecting the onset and relative degree of atherosclerosis in humans.
Creator: Shankar, Ravi, Florida Atlantic University
Date Issued: 1993-09
PURL: http://purl.flvc.org/fcla/dt/15858
Format: Document (PDF)

Title: High speed scaleable multiplier.
Creator: Shankar, Ravi, Florida Atlantic University
Date Issued: 2003-06
PURL: http://purl.flvc.org/fcla/dt/15828
Format: Document (PDF)

Title: Methods of detecting atherosclerosis while excluding motion artifacts.
Creator: Shankar, Ravi, Florida Atlantic University
Date Issued: 1994-03
PURL: http://purl.flvc.org/fcla/dt/15847
Format: Document (PDF)

Title: A Modeling Methodology for an RTOS.
Creator: Islam, Sifat, Shankar, Ravi, Florida Atlantic University
Abstract/Description: Enhanced system design productivity is key to satisfying time-to-market demands. One will have to exploit design reuse methodology to meet project schedule requirements. Integration of components often fails due to various concurrency violations. Concurrency issues arise when components executing in parallel share resources and interact with each other. Such a system may have intermittent, yet catastrophic failures, if these concurrency issues are not addressed properly. In this thesis, we...
Show moreEnhanced system design productivity is key to satisfying time-to-market demands. One will have to exploit design reuse methodology to meet project schedule requirements. Integration of components often fails due to various concurrency violations. Concurrency issues arise when components executing in parallel share resources and interact with each other. Such a system may have intermittent, yet catastrophic failures, if these concurrency issues are not addressed properly. In this thesis, we propose a methodology for developing concurrency compliant components from a requirement document. We have applied this methodology for developing process management and memory management aspects of a Real Time Operating System (RTOS). In this methodology, we start from a "customer' s" requirement document that is then mapped to activity diagram, swimlane diagram, class diagrams, and use case diagrams. To evolve a concurrency compliant design, we use the Message Sequence Chart plug-in for the Labeled Transition State Analyzer (LTSA). This plug-in lets us use Message Sequence Charts rather than coding in Finite State Processes (FSP). Later, we use MLDesigner to simulate our R TOS sub-system and demonstrate proper behavior of this sub-system.
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Date Issued: 2007
PURL: http://purl.flvc.org/fau/fd/FA00012528
Subject Headings: Computer architecture, Object-oriented programming (Computer science), Real-time programming, Operating systems (Computers)
Format: Document (PDF)

Title: DIGITAL PCM MF RECEIVER.
Creator: CHENTHANAKIJ, APICHAI., Florida Atlantic University, Shankar, Ravi
Abstract/Description: A PCM MF Receiver based on either analog or digital filters results in a fairly large chip. A recent publication attempts to address this issue by using certain approximations that replace multiplications with simple additions and subtractions. This results in a significantly smaller chip. In our research, we have further refined/changed the algorithms and approximations in order to reduce the chip size further and the chip count to one. A simulation model corresponding to this, written in...
Show moreA PCM MF Receiver based on either analog or digital filters results in a fairly large chip. A recent publication attempts to address this issue by using certain approximations that replace multiplications with simple additions and subtractions. This results in a significantly smaller chip. In our research, we have further refined/changed the algorithms and approximations in order to reduce the chip size further and the chip count to one. A simulation model corresponding to this, written in ISPS and Fortran, was extensively utilized to verify that the proposed receiver would meet and/or exceed all the commercial specifications. Subsequent to that, we initiated hardware design using structured methodologies. Hardware modules written in a high-level hardware description language have been simulated for functional validity. We expect to utilize mixed mode simulations and hierarchical design concepts in translating this high-level description to a hardware implementation on a semi-custom CMOS chip.
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Date Issued: 1987
PURL: http://purl.flvc.org/fcla/dt/14354
Subject Headings: Electric filters, Digital--Computer programs, Telephone
Format: Document (PDF)

Title: A DATA ACQUISITION AND PROCESSING SYSTEM FOR THE STUDY OF PERIPHERAL VASCULAR DYNAMICS.
Creator: CIKIKCI, ISMAIL OGUZ., Florida Atlantic University, Shankar, Ravi
Abstract/Description: In this study, electrical impedance plethysmograph was used to measure the nonlinear elastic properties of the leg arteries. Two methods were used. In method one, a pressure cuff was wrapped around the lower leg and the recordings were made from under the cuff. Also a second set of recordings were made at a site distal to the cuff, to determine the attenuation of blood pressure pulse by the cuff at cuff pressures above diastolic. In method 2 an Inverter was used and recordings were made from...
Show moreIn this study, electrical impedance plethysmograph was used to measure the nonlinear elastic properties of the leg arteries. Two methods were used. In method one, a pressure cuff was wrapped around the lower leg and the recordings were made from under the cuff. Also a second set of recordings were made at a site distal to the cuff, to determine the attenuation of blood pressure pulse by the cuff at cuff pressures above diastolic. In method 2 an Inverter was used and recordings were made from the same segment. Also recordings were made from the upper arm at the heart level to define the blood pressure pulse, that causes the volume change in the leg arteries. A wide range of pressures were used and V-P and compliance curves were calculated with both the methods. In order to improve the accuracy and reduce operator errors, a personal computer based data acquisition and processing system was developed.
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Date Issued: 1986
PURL: http://purl.flvc.org/fcla/dt/14338
Subject Headings: Arteries, Electronic data processing--Medicine, Diagnosis, Noninvasive
Format: Document (PDF)

Title: Digital implementation of Alopex: HDL simulation studies.
Creator: Freytag, Lynn R., Florida Atlantic University, Shankar, Ravi
Abstract/Description: Alopex is a stochastic algorithm used to solve optimization problems in various types of systems. This thesis describes behavioral and structural hardware-description-language models which were developed for a three-stage VLSI-implementable Alopex architecture. The architecture features an SIMD structure and no communication between processing elements (PEs). Several approximations and simplifications were tested using the models to achieve a simple PE architecture and to implement the...
Show moreAlopex is a stochastic algorithm used to solve optimization problems in various types of systems. This thesis describes behavioral and structural hardware-description-language models which were developed for a three-stage VLSI-implementable Alopex architecture. The architecture features an SIMD structure and no communication between processing elements (PEs). Several approximations and simplifications were tested using the models to achieve a simple PE architecture and to implement the algorithm using integer arithmetic. Simulations were conducted with numerical image input to check the validity of these changes, and the timing relationships between PEs and controllers were explored. The use of a hardware description language provided an easy way to investigate timing and make architectural changes. The algorithm was found to function correctly under the digital hardware constraints and simplifications. The timing results gave an indication of the execution time for each step and pointed out areas in which the architecture may need to be improved.
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Date Issued: 1990
PURL: http://purl.flvc.org/fcla/dt/14650
Subject Headings: Computer hardware description languages--Simulation methods
Format: Document (PDF)

Title: A VLSI NMOS IMPLEMENTATION OF A BUILDING BLOCK PROCESSOR USING CORDIC ALGORITHMS (ARRAY PROCESSOR).
Creator: GIVEN, RAYMOND E., Florida Atlantic University, Shankar, Ravi
Date Issued: 1985
PURL: http://purl.flvc.org/fcla/dt/14247
Subject Headings: Array processors, Signal processing
Format: Document (PDF)

Title: Feature extraction implementation for handwritten numeral recognition.
Creator: Banuru, Prashanth K., Florida Atlantic University, Shankar, Ravi
Abstract/Description: Feature extraction for handwritten character recognition has always been a challenging problem for investigators in the field. The problem gets worse due to large variations present for each type of input character. Our algorithm computes directional features for alphanumeric input mapped on to a hexagonal lattice. The algorithm implements size and scale invariance that is a requirement for achieving a reasonably good recognition rate. Functional performance has been verified for an hexagonal...
Show moreFeature extraction for handwritten character recognition has always been a challenging problem for investigators in the field. The problem gets worse due to large variations present for each type of input character. Our algorithm computes directional features for alphanumeric input mapped on to a hexagonal lattice. The algorithm implements size and scale invariance that is a requirement for achieving a reasonably good recognition rate. Functional performance has been verified for an hexagonal lattice mapped input on the data obtained from the US postal service handwritten character database. In this thesis, we implemented the algorithm in a Xilinx FPGA (XC4xxx series).
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Date Issued: 1994
PURL: http://purl.flvc.org/fcla/dt/15103
Subject Headings: Algorithms, Pattern recognition systems--Computer simulation, Optical character recognition devices--Computer simulation
Format: Document (PDF)

Title: A MICROPROCESSOR BASED DRUG INFUSION CONTROL SYSTEM, EMPLOYING A MODEL REFERENCE ADAPTIVE CONTROL ALGORITHM, TO REGULATE BLOOD PRESSURE IN INTENSIVE CARE UNIT PATIENTS.
Creator: HERNANDEZ, LEO., Florida Atlantic University, Shankar, Ravi
Abstract/Description: This microprocessor based drug infusion control system is intended to aid doctors and nurses in the care of critically ill cardiac patients. The patient's arterial blood pressure is monitored and the infusion rate of the vasodilator sodium nitroprusside is regulated based on a model reference adaptive control algorithm. The algorithm employs a reference model to approximate the patient drug response. The reference model output is compared with the patient blood pressure change and the...
Show moreThis microprocessor based drug infusion control system is intended to aid doctors and nurses in the care of critically ill cardiac patients. The patient's arterial blood pressure is monitored and the infusion rate of the vasodilator sodium nitroprusside is regulated based on a model reference adaptive control algorithm. The algorithm employs a reference model to approximate the patient drug response. The reference model output is compared with the patient blood pressure change and the adaptive controller parameters are changed bringing the patient drug response in closer agreement with the reference model. Drug infusion is digitally controlled by a microprocessor based system and employs a stepper motor driven peristaltic pump. Simulation studies have validated the system. Animal experiments and clinical studies will be conducted later.
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Date Issued: 1987
PURL: http://purl.flvc.org/fcla/dt/14415
Subject Headings: Blood pressure--Regulation, Drug infusion pumps
Format: Document (PDF)

Title: Handprinted character recognition and Alopex algorithm analysis.
Creator: Du, Jian., Florida Atlantic University, Shankar, Ravi
Abstract/Description: A novel neural network, trained with the Alopex algorithm to recognize handprinted characters, was developed in this research. It was constructed by an encoded fully connected multi-layer perceptron (EFCMP). It consists of one input layer, one intermediate layer, and one encoded output layer. The Alopex algorithm is used to supervise the training of the EFCMP. Alopex is a stochastic algorithm used to solve optimization problems. The Alopex algorithm has been shown to accelerate the rate of...
Show moreA novel neural network, trained with the Alopex algorithm to recognize handprinted characters, was developed in this research. It was constructed by an encoded fully connected multi-layer perceptron (EFCMP). It consists of one input layer, one intermediate layer, and one encoded output layer. The Alopex algorithm is used to supervise the training of the EFCMP. Alopex is a stochastic algorithm used to solve optimization problems. The Alopex algorithm has been shown to accelerate the rate of convergence in the training procedure. Software simulation programs were developed for training, testing and analyzing the performance of this EFCMP architecture. Several neural networks with different structures were developed and compared. Optimization of the Alopex algorithm was explored through simulations of the EFCMP training procedure with the use of different parametric values for Alopex.
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Date Issued: 1994
PURL: http://purl.flvc.org/fcla/dt/15012
Subject Headings: Algorithms, Neural networks (Computer science), Optical character recognition devices, Writing--Data processing, Image processing
Format: Document (PDF)

Title: Handwritten digit recognition using neural network integrated chips.
Creator: Bidari, Ravindra Chandrashekar., Florida Atlantic University, Shankar, Ravi
Abstract/Description: Development of a handwritten digit recognition system for real time applications is a feasible goal today due to the many advances pertinent to VLSI. In this research we address the issue of mapping our neural net classification algorithm to Intel's commercially available general purpose Neural Network Chip, 80170NX (ETANN). Most of the proposed techniques used for character recognition have been validated by our research group using various software and hardware simulation methods. The...
Show moreDevelopment of a handwritten digit recognition system for real time applications is a feasible goal today due to the many advances pertinent to VLSI. In this research we address the issue of mapping our neural net classification algorithm to Intel's commercially available general purpose Neural Network Chip, 80170NX (ETANN). Most of the proposed techniques used for character recognition have been validated by our research group using various software and hardware simulation methods. The objective of this thesis was to develop a practical hardware system to perform the final step of classification of handwritten digits in an Optical Character Recognition (OCR) system. Such a hardware implementation would increase the classification speed and also would permit testing in a real life application environment. An efficient mapping scheme was evolved to map the modules of a limited interconnect classification algorithm, CLUMP, to a minimum number of ETANN chips. The hardware modules to interface the ETANN chips to MC68000 education board have been developed and tested. The proposed system is estimated to process the features input in 336 $\mu$s, for our specific implementation, with 12 clock phases and 3 ETANN chips.
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Date Issued: 1992
PURL: http://purl.flvc.org/fcla/dt/14838
Subject Headings: Optical character recognition devices--Computer simulation, Pattern recognition systems--Computer simulation
Format: Document (PDF)

Title: Highly scalable multiplier.
Creator: Ajmera, Abhijit M., Florida Atlantic University, Shankar, Ravi
Abstract/Description: High speed low power scalable multiplier is needed in computation intensive DSP applications such as video and image compression algorithms. We used an algorithm that folds the larger bit-width operands so smaller bit-width multipliers can be used. Successive folding on operands can be done until a desired threshold is reached. This method has inherent advantages of reuse of optimized building blocks, dynamic reconfiguration, and low power. We implemented a hardware multiplier based on this...
Show moreHigh speed low power scalable multiplier is needed in computation intensive DSP applications such as video and image compression algorithms. We used an algorithm that folds the larger bit-width operands so smaller bit-width multipliers can be used. Successive folding on operands can be done until a desired threshold is reached. This method has inherent advantages of reuse of optimized building blocks, dynamic reconfiguration, and low power. We implemented a hardware multiplier based on this algorithm using Verilog hardware description language. Our results show that this multiplier exhibited significant power advantage over Array and Wallace Tree multipliers for comparable speeds, but had higher gate counts.
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Date Issued: 2003
PURL: http://purl.flvc.org/fcla/dt/13080
Subject Headings: Digital multipliers--Design and construction, Multipliers (Mathematical analysis), Verilog (Computer hardware description language)
Format: Document (PDF)

Title: Modeling multiple abstraction levels in SoC using SystemC.
Creator: Jillellamudi, Haritha., Florida Atlantic University, Shankar, Ravi
Abstract/Description: Technological advances are providing us with the capability to integrate more and more functionality into a single chip. This is leading to a new design paradigm, System On a Chip (SoC). SoC design brings with it new challenges and difficulties. Managing these challenges and complexity necessitate modeling of systems at a hierarchy of abstraction levels starting from System Level down to Register Transfer Level. Using a single language across all these levels would ensure that the models are...
Show moreTechnological advances are providing us with the capability to integrate more and more functionality into a single chip. This is leading to a new design paradigm, System On a Chip (SoC). SoC design brings with it new challenges and difficulties. Managing these challenges and complexity necessitate modeling of systems at a hierarchy of abstraction levels starting from System Level down to Register Transfer Level. Using a single language across all these levels would ensure that the models are consistent and error-free. SystemC is one such language that has the infrastructure for specifying the design at System level, Behavioral level and RT levels of abstraction. This thesis showcases the same using two design examples---Simplex Data Protocol and General Purpose Timer (GPT) peripheral. Coding style and level of detailing at different levels are shows. Process of refining from one level to another is illustrated. GPT peripheral module designed in this thesis work can be further reused as a timer library component in system architectures.
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Date Issued: 2003
PURL: http://purl.flvc.org/fcla/dt/13064
Subject Headings: Systems on a chip, Abstraction, C++ (Computer program language), System design
Format: Document (PDF)

Title: Software decomposition for multicore architectures.
Creator: Jain, Ankit., Florida Atlantic University, Shankar, Ravi
Abstract/Description: Current multicore processors attempt to optimize consumer experience via task partitioning and concurrent execution of these (sub)tasks on the cores. Conversion of sequential code to parallel and concurrent code is neither easy, nor feasible with current methodologies. We have developed a mapping process that synergistically uses top-down and bottom-up methodologies. This process is amenable to automation. We use bottom-up analysis to determine decomposability and estimate computation and...
Show moreCurrent multicore processors attempt to optimize consumer experience via task partitioning and concurrent execution of these (sub)tasks on the cores. Conversion of sequential code to parallel and concurrent code is neither easy, nor feasible with current methodologies. We have developed a mapping process that synergistically uses top-down and bottom-up methodologies. This process is amenable to automation. We use bottom-up analysis to determine decomposability and estimate computation and communication metrics. The outcome is a set of proposals for software decomposition. We then build abstract concurrent models that map these decomposed (abstract) software modules onto candidate multicore architectures; this resolves concurrency issues. We then perform a system level simulation to estimate concurrency gain and/or cost, and QOS (Qualify-of-Service) metrics. Different architectural combinations yield different QOS metrics; the requisite system architecture may then be chosen. We applied this 'middle-out' methodology to optimally map a digital camera application onto a processor with four cores.
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Date Issued: 2006
PURL: http://purl.flvc.org/fcla/dt/13349
Subject Headings: Optimal designs (Statistics), Software architecture, Software engineering, Computer architecture, System design, Computer networks--Security measures
Format: Document (PDF)

Title: A Collaborative Geospatial Shoreline Inventory Tool to Guide Coastal Development and Habitat Conservation.
Creator: Mitsova, Diana, Wissinger, Frank, Esnard, Ann-Margaret, Shankar, Ravi, Gies, Peter
Date Issued: 2013-05-13
PURL: http://purl.flvc.org/fau/fd/FAUIR000175
Format: Citation

Title: Bilingual Sentiment Analysis of Spanglish Tweets.
Creator: Serrano, Melissa, Shankar, Ravi, Florida Atlantic University, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Sentiment Analysis has been researched in a variety of contexts but in this thesis, the focus is on sentiment analysis in Twitter, which poses its own unique challenges such as the use of slang, abbreviations, emoticons, hashtags, and user mentions. The 140-character restriction on the length of tweets can also lead to text that is difficult even for a human to determine its sentiment. Specifically, this study will analyze sentiment analysis of bilingual (U.S. English and Spanish language)...
Show moreSentiment Analysis has been researched in a variety of contexts but in this thesis, the focus is on sentiment analysis in Twitter, which poses its own unique challenges such as the use of slang, abbreviations, emoticons, hashtags, and user mentions. The 140-character restriction on the length of tweets can also lead to text that is difficult even for a human to determine its sentiment. Specifically, this study will analyze sentiment analysis of bilingual (U.S. English and Spanish language) Tweets. The hypothesis here is that Bilingual sentiment analysis is more accurate than sentiment analysis in a single language (English or Spanish) when analyzing bilingual tweets. In general, currently sentiment analysis in bilingual tweets is done against an English dictionary. For each of the test cases in this thesis’ experiment we will use the Python NLTK sentiment package.
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Date Issued: 2017
PURL: http://purl.flvc.org/fau/fd/FA00004877, http://purl.flvc.org/fau/fd/FA00004877
Subject Headings: Twitter., Online social networks., Connotation (Linguistics), Mass media--Audiences., Spanish language--Usage.
Format: Document (PDF)

FAU Theses and Dissertations (36)	+ -
Florida Atlantic University Patents (5)	+ -
FAU College Collections (2)	+ -
FAU Undergraduate Student Research (1)	+ -

Integrated circuits--Very large scale integration (6)	+ -
Computer architecture (5)	+ -
Algorithms (4)	+ -
Optical character recognition devices (4)	+ -
Optical character recognition devices--Computer simulation (4)	+ -

Pattern recognition systems--Computer simulation (3)	+ -
System design (3)	+ -
Artificial intelligence (2)	+ -
Atherosclerosis--Animal models (2)	+ -
Computer network protocols (2)	+ -
Diagnosis, Noninvasive (2)	+ -
Impedance plethysmography (2)	+ -
Multiprocessors (2)	+ -
Neural computers (2)	+ -
Neural networks (Computer science) (2)	+ -
Operating systems (Computers) (2)	+ -
Pattern recognition systems (2)	+ -
Signal processing (2)	+ -
Abstraction (1)	+ -
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Applied mathematics (1)	+ -
Array processors (1)	+ -
Arteries (1)	+ -
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Blood pressure--Measurement (1)	+ -
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College students --Research --United States. (1)	+ -

Electronic Thesis or Dissertation (36)	+ -
patent (5)	+ -
article (1)	+ -
report (1)	+ -
symposium presentation (1)	+ -

Shankar, Ravi (44)	+ -
Florida Atlantic University (41)	+ -
College of Engineering and Computer Science (25)	+ -
Department of Computer and Electrical Engineering and Computer Science (24)	+ -
Esnard, Ann-Margaret (2)	+ -

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