Current Search:   Barrett, Raymond L. Jr. (x)

View All Items

  • CSV Spreadsheet
(1 - 3 of 3)
cochlea: A signal processing paradigm
Title
The cochlea: A signal processing paradigm.
Creator
Barrett, Raymond L. Jr., Florida Atlantic University, Erdol, Nurgun, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description
The cochlea provides frequency selectivity for acoustic input signal processing in mammals. The excellent performance of human hearing for speech processing leads to examination of the cochlea as a paradigm for signal processing. The components of the hearing process are examined and suitable models are selected for each component's function. The signal processing function is simulated by a computer program and the ensemble is examined for behavior and improvement. The models reveal that the...
Show moreThe cochlea provides frequency selectivity for acoustic input signal processing in mammals. The excellent performance of human hearing for speech processing leads to examination of the cochlea as a paradigm for signal processing. The components of the hearing process are examined and suitable models are selected for each component's function. The signal processing function is simulated by a computer program and the ensemble is examined for behavior and improvement. The models reveal that the motion of the basilar membrane provides a very selective low pass transmission characteristic. Narrowband frequency resolution is obtained from the motion by computation of spatial differences in the magnitude of the motion as energy propagates along the membrane. Basilar membrane motion is simulated using the integrable model of M. R. Schroeder, but the paradigm is useful for any model that exhibits similar high selectivity. Support is shown for an hypothesis that good frequency discrimination is possible without highly resonant structure. The nonlinear magnitude calculation is performed on signals developed without highly resonant structure, and differences in those magnitudes are signals shown to have good narrowband selectivity. Simultaneously, good transient behavior is preserved due to the avoidance of highly resonant structure. The cochlear paradigm is shown to provide a power spectrum with serendipitous good frequency selectivity and good transient response simultaneously.
Show less
Date Issued
1990
PURL
http://purl.flvc.org/fcla/dt/12251
Subject Headings
Engineering, Electronics and Electrical, Computer Science
Format
Document (PDF)
DCVS logic synthesis
Title
DCVS logic synthesis.
Creator
Xiao, Kang., Florida Atlantic University, Barrett, Raymond L. Jr., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description
Implementation of CMOS combinational logic with Differential Cascode Voltage Switch logic (DCVS) may have many advantages over the traditional CMOS logic approaches with respect to device count, layout density and timing. DCVS is an ideal target technology for a logic synthesis system in that it provides a complete function cover by providing the function and its complement simultaneously. DCVS is also more testable due to this. We have developed for IBM's DCVS technology a synthesis...
Show moreImplementation of CMOS combinational logic with Differential Cascode Voltage Switch logic (DCVS) may have many advantages over the traditional CMOS logic approaches with respect to device count, layout density and timing. DCVS is an ideal target technology for a logic synthesis system in that it provides a complete function cover by providing the function and its complement simultaneously. DCVS is also more testable due to this. We have developed for IBM's DCVS technology a synthesis algorithm and a new test generation approach, that are based on topologies rather than individual logic functions. We have found that 19 and 363 DCVS topologies can represent 256 and 65,536 functions, respectively, for the 3- and 4-varaible cases. Physical defect analysis was conducted with the aid of a building block approach to analyze the n-type logic tree and provides a basis for evolving hierarchical test pattern generation for the topologies.
Show less
Date Issued
1992
PURL
http://purl.flvc.org/fcla/dt/14850
Subject Headings
Integrated circuits--Very large scale integration--Data processing, Metal oxide semiconductors, Complementary, Computer-aided design, Electronic systems, Logic design--Data processing
Format
Document (PDF)
Electrical characterization of an innovative pad array carrier package for application specific electronic modules (ASEMs)
Title
Electrical characterization of an innovative pad array carrier package for application specific electronic modules (ASEMs).
Creator
Nagaraja, Padma S., Florida Atlantic University, Barrett, Raymond L. Jr., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description
Pad Array Carrier (PAC) packaging is used for surface mounting of modules on printed circuit cards. The package described in this study has an added feature that allows for the testing of the package through the holes laid along the periphery of the package board. MAGIC was used in the design and layout of an 8 x 8 array size PAC. Two key contributors to electrical noise in the package, viz., cross talk and signal reflections were analyzed. Transmission line models were developed for...
Show morePad Array Carrier (PAC) packaging is used for surface mounting of modules on printed circuit cards. The package described in this study has an added feature that allows for the testing of the package through the holes laid along the periphery of the package board. MAGIC was used in the design and layout of an 8 x 8 array size PAC. Two key contributors to electrical noise in the package, viz., cross talk and signal reflections were analyzed. Transmission line models were developed for analyzing these parameters. HSPICE and HP 85150B Microwave Design Systems (MDS) were used to simulate the transmission line models to evaluate the effects of cross talk and signal reflections on the package board. The performance of the package for the speed and maintenance of signal integrity was evaluated. Guidelines specifying the physical geometry limitations for line length, line width, line spacing, and layout configurations required to meet specific noise budget (cross talk and signal reflection considerations) were established.
Show less
Date Issued
1992
PURL
http://purl.flvc.org/fcla/dt/14856
Subject Headings
Electronic packaging, Multichip modules (Microelectronics)
Format
Document (PDF)