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Title: Infrastructure to model complex systems: hydrological modeling.
Creator: Wissinger, Frank, Shankar, Ravi, Florida Atlantic University, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: This research proposes an Infrastructure to model complex systems for hydrological modeling. Currently, the three main hydrological packages are: i) SEAWAT (modeling groundwater flow); ii) HECRAS (modeling surface water flow); iii) HEC-HMS (modeling atmospheric water flow). Each of these models is self-contained and has a different timescale and simulation speed. Consequently, any integrated model will only run as fast as the slowest of the models. This makes it difficult to provide reliable...
Show moreThis research proposes an Infrastructure to model complex systems for hydrological modeling. Currently, the three main hydrological packages are: i) SEAWAT (modeling groundwater flow); ii) HECRAS (modeling surface water flow); iii) HEC-HMS (modeling atmospheric water flow). Each of these models is self-contained and has a different timescale and simulation speed. Consequently, any integrated model will only run as fast as the slowest of the models. This makes it difficult to provide reliable and dynamic information on water levels and water availability for a given geographical region in a timely manner. The goal of this research is to facilitate the integration of multiple hydrological models from different hydrological packages by applying Electronic Design Automation (EDA) methodologies, including System Level Design (SLD) methodology, SystemC-AMS language, Python language and libraries (numpy, Statsmodels, and ctypes). The EDA methodology brings in the additional advantage of significantly improved simulation speed. The Infrastructure to Model Complex Systems applications is demonstrated using the following SEAWAT benchmark problems: i) Case 1; ii) Henry; iii) Elder problem. Simulation results from the aforementioned benchmarks are analyzed and discussed. Lastly, future research work is presented.
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Date Issued: 2014
PURL: http://purl.flvc.org/fau/fd/FA00004338, http://purl.flvc.org/fau/fd/FA00004338
Subject Headings: Floodplain management, Groundwater -- Environmental aspects, Groundwater flow -- Computer simulation., Water resources development
Format: Document (PDF)

Title: Racial Inequalities in America: Examining Socieoeconomic Statistics Using the Semantic Web.
Creator: Terrell, David J, Shankar, Ravi, Florida Atlantic University, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: The visualization of recent episodes regarding apparently unjustifiable deaths of minorities, caused by police and federal law enforcement agencies, has been amplified through today's social media and television networks. Such events may seem to imply that issues concerning racial inequalities in America are getting worse. However, we do not know whether such indications are factual; whether this is a recent phenomenon, whether racial inequality is escalating relative to earlier decades, or...
Show moreThe visualization of recent episodes regarding apparently unjustifiable deaths of minorities, caused by police and federal law enforcement agencies, has been amplified through today's social media and television networks. Such events may seem to imply that issues concerning racial inequalities in America are getting worse. However, we do not know whether such indications are factual; whether this is a recent phenomenon, whether racial inequality is escalating relative to earlier decades, or whether it is better in certain regions of the nation compared to others. We have built a semantic engine for the purpose of querying statistics on various metropolitan areas, based on a database of individual deaths. Separately, we have built a database of demographic data on poverty, income, education attainment, and crime statistics for the top 25 most populous metropolitan areas. These data will ultimately be combined with government data to evaluate this hyp othesis, and provide a tool for predictive analytics. In this thesis, we will provide preliminary results in that direction. The methodology in our research consisted of multiple steps. We initially described our requirements and drew data from numerous datasets, which contained information on the 23 highest populated Metropolitan Statistical Areas in the United States. After all of the required data was obtained we decomposed the Metropolitan Statistical Area records into domain components and created an Ontology/Taxonomy via Protege to determine an hierarchy level of nouns towards identifying significant keywords throughout the datasets to use as search queries. Next, we used a Semantic Web implementation accompanied with Python programming language, and FuXi to build and instantiate a vocabulary. The Ontology was then parsed for the entered search query and returned corresponding results providing a semantically organized a nd relevant output in RDF/XML format.
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Date Issued: 2015
PURL: http://purl.flvc.org/fau/fd/FA00004550, http://purl.flvc.org/fau/fd/FA00004550
Subject Headings: Data mining, Education -- Demographic aspects -- United States -- Statistics, Minorities -- United States -- Social conditions, Minorities -- United States -- Statistics, Race -- United States -- Statistics, Semantic Web, United States -- Ethnic relations -- Statistics, United States -- Race relations -- Statistics
Format: Document (PDF)

Title: Low Cost Robotic Car as a Way to Teach Mathematics.
Creator: Aguerrevere, Santiago Andres, Shankar, Ravi, Florida Atlantic University, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: This report describes the development of a low cost open source semiautonomous robotic car and a way to communicate with it. It is a continuation of prior research done by other students at FAU and published in recent ASEE conferences. The objective of this project was the development of a new robotic platform with improved precision over the original, while still keeping the cost down. It was developed with the aim to allow a hands-on approach to the teaching of mathematics topics that are...
Show moreThis report describes the development of a low cost open source semiautonomous robotic car and a way to communicate with it. It is a continuation of prior research done by other students at FAU and published in recent ASEE conferences. The objective of this project was the development of a new robotic platform with improved precision over the original, while still keeping the cost down. It was developed with the aim to allow a hands-on approach to the teaching of mathematics topics that are taught in the K-12 syllabus. Improved robustness and reliability of the robotic platform for visually solving math problems was achieved using a combination of PID loops to keep track of distance and rotation. The precision was increased by changing the position of the encoders to the shafts of each motor. A mobile application was developed to allow the student to draw the geometric shapes on the screen before the car draws them. The mobile application consists of two parts, the canvas that the user uses to draw the figure and the configure section that lets the user change the parameters of the controller. Results show that the robot can draw standard geometric and complex geometric shapes. It has high precision and sufficient accuracy, the accuracy can be improved with some mechanical adjustments. During testing a Pythagorean triangle was drawn to show visually the key mathematics concept. The eventual goal of this project will be a K-12 class room study to obtain the feedback of the teachers and students on the feasibility of using a robotic car to teach math. Subsequent to that necessary changes will be made to manufacture a unit that is easy to assemble by the teacher.
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Date Issued: 2016
PURL: http://purl.flvc.org/fau/fd/FA00004712, http://purl.flvc.org/fau/fd/FA00004712
Subject Headings: Adaptive control systems, Applied mathematics, Artificial intelligence, Computers, Special purpose, Mathematics -- Study and teaching, User interfaces (Computer systems)
Format: Document (PDF)

Title: Martial Arts as a markup language.
Creator: Vo, Thomas, Shankar, Ravi, Florida Atlantic University, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: This thesis describes the modeling of Martial Arts as a markup language. Up until now Martial Arts has already been documented in books, videos, tradition and other methods. Though to represent Martial Arts knowledge consistently and uniformly in a digital era, we introduce the Martial Arts Markup Language (MAML), which is based on XML. Because XML provides a standardized, serializable and portable format, MAML also enables sharing among students, teachers and their peers across different...
Show moreThis thesis describes the modeling of Martial Arts as a markup language. Up until now Martial Arts has already been documented in books, videos, tradition and other methods. Though to represent Martial Arts knowledge consistently and uniformly in a digital era, we introduce the Martial Arts Markup Language (MAML), which is based on XML. Because XML provides a standardized, serializable and portable format, MAML also enables sharing among students, teachers and their peers across different platforms, media and networks. MAML provides the ability, with appropriate XML tools, to document a Martial Arts style in a structured way. To achieve this, we first analyze the aspects that comprise Martial Arts; and how its states and processes relate to one another. We model in MAML describing the stances, transitions, punches, blocks, techniques, combinations, reactions and patterns used in Martial Arts. We discuss the implementation of MAML by observing and extracting the definable aspects in existing Martial Art Instructive Documents. The MAML Schema assures that the details of a Martial Arts Style’s elements are consistent. Current simulation efforts will be explained as well as areas for future development. We have described Martial Arts by observing what has already been done and creating a structured standard to document them. We hope to enable practitioners’ abilities to learn from and develop their arts by providing a resource in which they can interact with.
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Date Issued: 2014
PURL: http://purl.flvc.org/fau/fd/FA00004232, http://purl.flvc.org/fau/fd/FA00004232
Subject Headings: Martial arts--Digital techniques., Human mechanics--Digital techniques., Document markup langauges., Computer graphics., XML (Document markup language), MAML (Document markup language), Labanotation.
Format: Document (PDF)

Title: Microservices-based approach for Healthcare Cybersecurity.
Creator: Trivedi, Ohm H., Shankar, Ravi, Florida Atlantic University, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Healthcare organizations, realizing the potential of the Internet of Things (IoT) technology, are rapidly adopting the technology to bring signi cant improvements in the quality and e ectiveness of the service. However, these smart and interconnected devices can act as a potential \back door" into a hospital's IT network, giving attack- ers access to sensitive information. As a result, cyber-attacks on medical IoT devices have been increasing since the last few years. It is a growing concern...
Show moreHealthcare organizations, realizing the potential of the Internet of Things (IoT) technology, are rapidly adopting the technology to bring signi cant improvements in the quality and e ectiveness of the service. However, these smart and interconnected devices can act as a potential \back door" into a hospital's IT network, giving attack- ers access to sensitive information. As a result, cyber-attacks on medical IoT devices have been increasing since the last few years. It is a growing concern for all the stakeholders involved, as the impact of such attacks is not just monetary or privacy loss, but the lives of many patients are also at risk. Considering the various kinds of IoT devices one may nd connected to a hospital's network, traditional host-centric security solutions (e.g. antivirus, software patches) are at odds with realistic IoT infrastructure (e.g. constrained hardware, lack of proper built-in security measures). There is a need for security solutions which consider the challenges of IoT devices like heterogeneity of technology and protocols used, limited resources in terms of battery and computation power, etc. Accordingly, the goals of this thesis have been: (1) to provide an in-depth understanding of vulnerabilities of medical IoT devices; (2) to in- troduce a novel approach which uses a microservices-based framework as an adaptive and agile security solution to address the issue. The thesis focuses on OS Fingerprint- ing attacks because of its signi cance for attackers to understand a target's network. In this thesis, we developed three microservices, each one designed to serve a speci c functionality. Each of these microservices has a small footprint with RAM usage of approximately 50 MB. We also suggest how microservices can be used in a real-life scenario as a software-based security solution to secure a hospital's network consisting of di erent IoT devices.
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Date Issued: 2018
PURL: http://purl.flvc.org/fau/fd/FA00013140
Subject Headings: Cybersecurity, Healthcare, Internet of things--Security measures, Medical care--Information technology--Security measures
Format: Document (PDF)

Title: Alopex for handwritten digit recognition: Algorithmic verifications.
Creator: Martin, Gregory A., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Alopex is a biologically influenced computation paradigm that uses a stochastic procedure to find the global optimum of linear and nonlinear functions. It maps to a hierarchical SIMD (Single-Instruction-Multiple-Data) architecture with simple neuronal processing elements (PE's), therefore the large amount of interconnects in other types of neural networks are not required and more efficient utilization of chip level and board level "real estate" is realized. In this study, verifications were...
Show moreAlopex is a biologically influenced computation paradigm that uses a stochastic procedure to find the global optimum of linear and nonlinear functions. It maps to a hierarchical SIMD (Single-Instruction-Multiple-Data) architecture with simple neuronal processing elements (PE's), therefore the large amount of interconnects in other types of neural networks are not required and more efficient utilization of chip level and board level "real estate" is realized. In this study, verifications were performed on the use of a simplified Alopex algorithm in handwritten digit recognition with the intent that the verified algorithm be digitally implementable. The inputs to the simulated Alopex hardware are a set of 32 features extracted from the input characters. Although the goal of verifying the algorithm was not achieved, a firm direction for future studies has been established and a flexible software model for these future studies is available.
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Date Issued: 1992
PURL: http://purl.flvc.org/fcla/dt/14842
Subject Headings: Algorithms--Data processing, Stochastic processes
Format: Document (PDF)

Title: Design of analog building blocks useful for artificial neural networks.
Creator: Renavikar, Ajit Anand., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Software simulations of a scaleable VLSI implementable architecture and algorithm for character recognition by a research group at Florida Atlantic University (FAU) have shown encouraging results. We address here hardware implementation issues pertinent to the classification phase of character recognition. Using the digit classification techniques developed at FAU as a foundation, we have designed and simulated general purpose building blocks useful for a possible implementation of a Digital ...
Show moreSoftware simulations of a scaleable VLSI implementable architecture and algorithm for character recognition by a research group at Florida Atlantic University (FAU) have shown encouraging results. We address here hardware implementation issues pertinent to the classification phase of character recognition. Using the digit classification techniques developed at FAU as a foundation, we have designed and simulated general purpose building blocks useful for a possible implementation of a Digital & Analog CMOS VLSI chip that is suitable for a variety of artificial neural network (ANN) architectures. HSPICE was used to perform circuit-level simulations of the building blocks. We present here the details of implementation of the recognition chip including the architecture, circuit design and the simulation results.
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Date Issued: 1996
PURL: http://purl.flvc.org/fcla/dt/15328
Subject Headings: Neural networks (Computer science), Artificial intelligence, Optical character recognition devices, Pattern recognition systems
Format: Document (PDF)

Title: Design of a high signal to noise ratio electrical impedance plethysmograph.
Creator: Urso, Alessio Francesco., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: We have developed a high signal to noise ratio automatically resetting electrical impedance plethysmograph for noninvasive determination of blood pressure in pigeons. Pigeons are finding increased use as an economical and appropriate animal model for the study of human atherosclerosis. The impedance plethysmograph obtains the pulsatile arterial volume change as an impedance pulse. Nyboer's equation may then be used to extract the arterial volume change from the impedance pulse. The designed...
Show moreWe have developed a high signal to noise ratio automatically resetting electrical impedance plethysmograph for noninvasive determination of blood pressure in pigeons. Pigeons are finding increased use as an economical and appropriate animal model for the study of human atherosclerosis. The impedance plethysmograph obtains the pulsatile arterial volume change as an impedance pulse. Nyboer's equation may then be used to extract the arterial volume change from the impedance pulse. The designed impedance plethysmograph has a sensitivity of 430 mV/m$\Omega$ and a noise level of 0.12 m$\Omega$ peak-to-peak, significantly better than systems reported earlier. Refinements to further enhance the performance are also presented.
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Date Issued: 1990
PURL: http://purl.flvc.org/fcla/dt/14609
Subject Headings: Impedance plethysmography, Atherosclerosis--Animal models, Blood pressure--Measurement
Format: Document (PDF)

Title: Digital implementation issues of artificial neural networks.
Creator: Pesulima, Edward Elisha., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Recent years have seen the renaissance of the neural network field. Significant advances in our understanding of neural networks and its possible applications necessitate investigations into possible implementation strategies. Among the presently available implementation medium, digital VLSI hardware is one of the more promising because of its maturity and availability. We discuss various issues connected with implementing neural networks in digital VLSI hardware. A new sigmoidal transfer...
Show moreRecent years have seen the renaissance of the neural network field. Significant advances in our understanding of neural networks and its possible applications necessitate investigations into possible implementation strategies. Among the presently available implementation medium, digital VLSI hardware is one of the more promising because of its maturity and availability. We discuss various issues connected with implementing neural networks in digital VLSI hardware. A new sigmoidal transfer function is proposed with that implementation in mind. Possible realizations of the function for stochastic and deterministic neural networks are discussed. Simulation studies of applying neural networks in constraint optimization and learning problems are carried out. These simulations were performed strictly in integer arithmetic. Simulation results provides an encouraging outlook for implementing these neural network applications in digital VLSI hardware. Important results concerning the sizes of various network values were found for learning algorithms.
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Date Issued: 1990
PURL: http://purl.flvc.org/fcla/dt/14646
Subject Headings: Neural computers, Neural computers--Circuits, Integrated circuits--Very large scale integration
Format: Document (PDF)

Title: PIREN(copyright): A heuristic algorithm for standard cell placement.
Creator: Horvath, Elizabeth Iren., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: The placement problem is an important part in the design process of VLSI chips. It is necessary to have a proper placement so that all connections between modules in a chip can be routed in a minimum area without violating any physical or electrical constraints. Current algorithms either do not give optimum solutions, are computationally slow, or are difficult to parallelize. PIREN(copyright) is a parallel implementation of a force directed algorithm which seeks to overcome the large amount...
Show moreThe placement problem is an important part in the design process of VLSI chips. It is necessary to have a proper placement so that all connections between modules in a chip can be routed in a minimum area without violating any physical or electrical constraints. Current algorithms either do not give optimum solutions, are computationally slow, or are difficult to parallelize. PIREN(copyright) is a parallel implementation of a force directed algorithm which seeks to overcome the large amount of computer time associated with solving the placement problem. Each active processor in the massively parallel SIMD machine, the MasPar MP-2.2, can perform in parallel the computation necessary to place cells in an optimum location relative to one another based upon the connectivity between cells. This is due to a salient feature of the serial algorithm which allows multiple permutations to be made simultaneously on all modules in order to minimize the objective function. The serial implementation of PIREN(copyright) compares favorably in both run time and layout quality to the simulated annealing based algorithm, TimberWolf3.2$\sp\copyright$. The parallel implementation on the MP-2.2 has a speedup of 4.5 to 58.0 over the serial version of PIREN$\sp\copyright$ running of the VAX 6320, while producing layouts for several MCNC benchmarks which are of the same quality as those produced by the serial implementation.
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Date Issued: 1992
PURL: http://purl.flvc.org/fcla/dt/12301
Subject Headings: Integrated circuits--Very large scale integration, Algorithms
Format: Document (PDF)

Title: QoS Driven Communication Backbone for NOC Based Embedded Systems.
Creator: Agarwal, Ankur, Shankar, Ravi, Florida Atlantic University, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: With the increasing complexity of the system design, it has become very critical to enhance system design productivity to meet with the time-to-market demands. Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogeneous multiprocessor architecture platform. Such a multiprocessor system on chip (MPSoC) platform has set new innovative trends for the real-time systems and...
Show moreWith the increasing complexity of the system design, it has become very critical to enhance system design productivity to meet with the time-to-market demands. Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogeneous multiprocessor architecture platform. Such a multiprocessor system on chip (MPSoC) platform has set new innovative trends for the real-time systems and system on Chip (SoC) designers. The consequences of this trend imply the shift in concern from computation and sequential algorithms to modeling concurrency, synchronization and communication in every aspect of hardware and software co-design and development. Some of the main problems in the current deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm arise from non scalable wire delays, errors in signal integrity and un-synchronized communication. These problems have been addressed by the use of packet switched Network on Chip (NOC) architecture for future SoCs and thus, real-time systems. Such a NOC based system should be able to support different levels of quality of service (QoS) to meet the real time systems requirements. It will further help in enhancing the system productivity by providing a reusable communication backbone. Thus, it becomes extremely critical to properly design a communication backbone (CommB) for NOC. Along with offering different levels of QoS, CommB is responsible directing the flow of data from one node to another node through routers, allocators, switches, queues and links. In this dissertation I present a reusable component based, design of CommB, suitable for embedded applications, which supports three types of QoS (real-time, multi-media and control applications).
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Date Issued: 2006
PURL: http://purl.flvc.org/fau/fd/FA00012566
Subject Headings: Computer networks--Quality control, Data transmission systems, Embedded computer systems--Quality control, Interconnects (Integrated circuit technology)
Format: Document (PDF)

Title: System level simulations of an optical character recognition system.
Creator: Phadnis, Mangirish Jayawant., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Optical Character Recognition systems have many applications in today's world of electronic computing. Various software implementations are currently being used. This thesis evolves a massively parallel hardware implementation for the system that is VLSI scaleable and may lead to substantial increase in the processing speed. This system involves various stages for preprocessing and processing of the image implemented with SIMD architecture, using simple processing elements and near neighbor...
Show moreOptical Character Recognition systems have many applications in today's world of electronic computing. Various software implementations are currently being used. This thesis evolves a massively parallel hardware implementation for the system that is VLSI scaleable and may lead to substantial increase in the processing speed. This system involves various stages for preprocessing and processing of the image implemented with SIMD architecture, using simple processing elements and near neighbor communications. The architecture evolved is simulated using the Verilog Hardware Description Language. This project should provide a framework for a massively parallel processing architecture for such systems. It is expected that this project will lead to the design and implementation of a real time system.
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Date Issued: 1994
PURL: http://purl.flvc.org/fcla/dt/15106
Subject Headings: Optical character recognition devices, Integrated circuits--Very large scale integration, Optical scanners, Image processing--Digital techniques
Format: Document (PDF)

Title: A VLSI implementation of a hexagonal topology CCD image sensor.
Creator: Madabushi, Vasudhevan., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: In this thesis we report a VLSI design implementation of an application specific, full-frame architecture CCD image sensor for a handwritten Optical Character Recognition system. The design is targeted to the MOSIS 2mu, 2-poly/ 2-metal n-buried channel CCD/CMOS technology. The front side illuminated CCD image sensor uses a transparent polysilicon gate structure and is comprised of 84 (H) x 100 (V) pixels arranged in a hexagonal lattice structure. The sensor has unit pixel dimensions of 18...
Show moreIn this thesis we report a VLSI design implementation of an application specific, full-frame architecture CCD image sensor for a handwritten Optical Character Recognition system. The design is targeted to the MOSIS 2mu, 2-poly/ 2-metal n-buried channel CCD/CMOS technology. The front side illuminated CCD image sensor uses a transparent polysilicon gate structure and is comprised of 84 (H) x 100 (V) pixels arranged in a hexagonal lattice structure. The sensor has unit pixel dimensions of 18 lambda (H) x 16 lambda (V). A second layer of metal is used for shielding certain areas from incident light, and the effective pixel photosite area is 8 lambda x 8 lambda. The imaging pixels use a 3-phase structure (with an innovative addressing scheme for the hexagonal lattice) for image sensing and horizontal charge shift. Columns of charge are shifted into the vertical 2-phase CCD shift registers, which shift the charge out serially at high speed. The chip has been laid out on the 'tinychip' (2250 mu m x 2220 (mu m) pad frame and fabrication through MOSIS is planned next.
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Date Issued: 1995
PURL: http://purl.flvc.org/fcla/dt/15123
Subject Headings: Integrated circuits--Very large scale integration, Optical character recognition devices, Pattern recognition systems, Imaging systems
Format: Document (PDF)

Title: A VLSI implementable handwritten digit recognition system using artificial neural networks.
Creator: Agba, Lawrence C., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: A VLSI implementable feature extraction scheme, and two VLSI implementable algorithms for feature classification that should lead to a practical handwritten digit recognition system are proposed. The feature extraction algorithm exploits the concept of holon dynamics. Holons can be regarded as a group of cooperative processors with self-organizing property. Two types of artificial neural network-based classifiers have been evolved to classify these features. The United States Post Office...
Show moreA VLSI implementable feature extraction scheme, and two VLSI implementable algorithms for feature classification that should lead to a practical handwritten digit recognition system are proposed. The feature extraction algorithm exploits the concept of holon dynamics. Holons can be regarded as a group of cooperative processors with self-organizing property. Two types of artificial neural network-based classifiers have been evolved to classify these features. The United States Post Office handwritten digit database was used to train and test these networks. The first type of classifier system used limited interconnect multi-layer perceptron (LIMP) modules in a hierarchical configuration. Each classifier in this system was independently trained and designated to recognize a particular digit. A maximum of sixty-one digits were used to train and 464 digits which included the training set were used to test the classifiers. A cumulative performance of 93.75% (correctly recognized digits) was recorded. The second classifier system consists of a cluster of small multi-layer perceptron (CLUMP) networks. Each cell in this system was independently trained to trace the boundary between two or more digits in the recognition plane. A combination of these cells distinguish a digit from the rest. This system was trained with 1796 digits and tested on 1918 different set of digits. On the training set a performance of 95.55% was recorded while 79.35% resulted from the test data. These results, which are expected to further improve, are superior to those obtained by other researchers on the same database. This technique of digit recognition is general enough for application in the development of a universal alphanumeric recognition system. A hybrid VLSI system consisting of both analog and digital circuitry, and utilizing both Bi-CMOS and switched capacitor technologies has been designed. The design is intended for implementation with the current MOSIS 2 $\mu$m, double poly, double metal, and p-well CMOS technology. The integrated circuit is such that both classifier systems can be realized using the same chip.
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Date Issued: 1990
PURL: http://purl.flvc.org/fcla/dt/12260
Subject Headings: Optical character recognition devices--Computer simulation, Pattern recognition systems--Computer simulation
Format: Document (PDF)

Title: A VLSI implementable thinning algorithm.
Creator: Zhang, Wei, Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Thinning is a very important step in a Character Recognition System. This thesis evolves a thinning algorithm that can be hardware implemented to improve the speed of the process. The software thinning algorithm features a simple set of rules that can be applied on both hexagonal and orthogonal character images. The hardware architecture features the SIMD structure, simple processing elements and near neighbor communications. The algorithm was simulated against the U.S. Postal Service...
Show moreThinning is a very important step in a Character Recognition System. This thesis evolves a thinning algorithm that can be hardware implemented to improve the speed of the process. The software thinning algorithm features a simple set of rules that can be applied on both hexagonal and orthogonal character images. The hardware architecture features the SIMD structure, simple processing elements and near neighbor communications. The algorithm was simulated against the U.S. Postal Service Character Database. The architecture, evolved with consideration of both the software constraints and the physical layout limitations, was simulated using VHDL hardware description language. Subsequent to VLSI design and simulations the chip was fabricated. The project provides for a feasibility study in utilizing the parallel processor architecture for the implementation of a parallel image thinning algorithm. It is hoped that such a hardware implementation will speed up the processing and lead eventually to a real time system.
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Date Issued: 1992
PURL: http://purl.flvc.org/fcla/dt/14837
Subject Headings: Optical character recognition devices--Computer simulation, Algorithms, Integrated circuits--Very large scale integration
Format: Document (PDF)

Title: The design and implementation of a simple master/slave interprocess-communication module.
Creator: Mandadi, Sanjay Reddy, Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: We explored the portability of various OS concepts to silicon. We wish to develop intellectual property blocks of various OS concepts, so that an embedded system designer has the option to mix and match. As a first step we have looked at inter-process communication (IPC) and Process Scheduling. We have implemented simple hardware building blocks for these. In our problem we utilize two processors, one each assigned as Master and Slave. Master is in control and implements the OS algorithms,...
Show moreWe explored the portability of various OS concepts to silicon. We wish to develop intellectual property blocks of various OS concepts, so that an embedded system designer has the option to mix and match. As a first step we have looked at inter-process communication (IPC) and Process Scheduling. We have implemented simple hardware building blocks for these. In our problem we utilize two processors, one each assigned as Master and Slave. Master is in control and implements the OS algorithms, while the Slave executes the user/application code. We show that these OS building blocks can be implemented in the hardware. Future effort of our group is to build a portfolio of OS IP blocks and explore optimization for various applications.
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Date Issued: 2000
PURL: http://purl.flvc.org/fcla/dt/12690
Subject Headings: Operating systems (Computers), Computer networks--Design and construction, Multiprocessors
Format: Document (PDF)

Title: A model to evaluate the effect of interference on Bluetooth functionality.
Creator: Puttamreddy, Jaideepesh., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: We explored the possible effects of various interferences on Bluetooth devices in the ISM band. We developed a model of Bluetooth and interference from sources such as WLAN devices and Microwave oven, and evaluate the functionality of Bluetooth in the presence of these interferences. As a first step we created Bluetooth, WLAN and Microwave oven models using SPW (Signal Processing Workstation). In our exploration, we undertake three cases: (1) When the Bluetooth is in the presence of only...
Show moreWe explored the possible effects of various interferences on Bluetooth devices in the ISM band. We developed a model of Bluetooth and interference from sources such as WLAN devices and Microwave oven, and evaluate the functionality of Bluetooth in the presence of these interferences. As a first step we created Bluetooth, WLAN and Microwave oven models using SPW (Signal Processing Workstation). In our exploration, we undertake three cases: (1) When the Bluetooth is in the presence of only noises in the channel; (2) When the Bluetooth is in the presence of Microwave oven interference; (3) When the Bluetooth is in the presence of WLAN interference. We show that these models can be used to analyze the interferences on the Bluetooth in the ISM band. Future efforts of our group will be to analyze this Bluetooth model with combined interference from all the sources, to come up with possible solutions to reduce the effect of these interferences.
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Date Issued: 2001
PURL: http://purl.flvc.org/fcla/dt/12800
Subject Headings: Bluetooth technology, Computer network protocols, Telecommunication--Equipment and supplies
Format: Document (PDF)

Title: Survey of design techniques for signal integrity.
Creator: Karnati, Raghuveer., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Signal Integrity is a major bottleneck for DSM designs. Signal integrity refers to wide variety of problems, which leads to misconception. Signal integrity causes delay or noise at the high-level, but this boils down to resistance, capacitance and inductance (RLC) at circuit level. Several analysis and reduction techniques were proposed for reducing these effects on signal integrity. This work solves the misconception by encompassing different problems Chat effect signal integrity and can be...
Show moreSignal Integrity is a major bottleneck for DSM designs. Signal integrity refers to wide variety of problems, which leads to misconception. Signal integrity causes delay or noise at the high-level, but this boils down to resistance, capacitance and inductance (RLC) at circuit level. Several analysis and reduction techniques were proposed for reducing these effects on signal integrity. This work solves the misconception by encompassing different problems Chat effect signal integrity and can be good reference for a integrated circuit designer. The objective is to analyze these modeling methods, reduction techniques, tools and make recommendations that aids in developing a methodology for perfect design closure with an emphasis on signal integrity. These recommendations would form a basis for developing a methodology to analyze interference effects at higher levels of abstraction.
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Date Issued: 2003
PURL: http://purl.flvc.org/fcla/dt/13065
Subject Headings: Integrated circuits--Design and construction, Signal processing, Electronic circuit design
Format: Document (PDF)

Title: SEMI-CUSTOM DESIGN OF A MICROPROGRAMMED TESTABLE REDUCED INSTRUCTION SET COMPUTER.
Creator: POENATEETAI, VIWAT., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: The concept of a Reduced Instruction Set Computer (RISC) has evolved out of a desire to enhance the performance of a computer. We present here a detailed design of a Testable Reduced Instruction Set Computer (TRISC) that utilizes a Multiple Register Set. Level Sensitive Scan Design (LSSD) is used to incorporate testability into our design. We first evolved a functional description of the design using Digital Design Language (DDL) a hardware programming language. We then entered the schematic...
Show moreThe concept of a Reduced Instruction Set Computer (RISC) has evolved out of a desire to enhance the performance of a computer. We present here a detailed design of a Testable Reduced Instruction Set Computer (TRISC) that utilizes a Multiple Register Set. Level Sensitive Scan Design (LSSD) is used to incorporate testability into our design. We first evolved a functional description of the design using Digital Design Language (DDL) a hardware programming language. We then entered the schematic of the design into Daisy's Logician V, a CAD/CAE workstation, using NCR CMOSII Digital Standard Cell Library. We then performed a unit delay simulation on the hierarchical design database to ascertain the logical functioning of the system.
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Date Issued: 1986
PURL: http://purl.flvc.org/fcla/dt/14284
Subject Headings: Computer architecture, Integrated circuits--Very large scale integration
Format: Document (PDF)

Title: SHINE: An integrated environment for software hardware co-design.
Creator: Jayadevappa, Suryaprasad., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: The rapid evolution of silicon technology has brought exponential benefits in cost, scale of integration, power per function, size per function and speed. The ability to place multiple function "systems" on a single silicon chip, reduce development cycle while increasing product functionality, performance and quality. With this increased complexity, ability to model at high level of abstraction becomes crucial. Also, the fact that no known existing complete system on chip design packages with...
Show moreThe rapid evolution of silicon technology has brought exponential benefits in cost, scale of integration, power per function, size per function and speed. The ability to place multiple function "systems" on a single silicon chip, reduce development cycle while increasing product functionality, performance and quality. With this increased complexity, ability to model at high level of abstraction becomes crucial. Also, the fact that no known existing complete system on chip design packages with perfect tools, models, and formalisms further slows down and complicates the development. This dissertation provides an integrated environment for hardware software co-design at a high level of abstraction. We have developed a SystemC based cockpit for this purpose. The cockpit, known as SHINE consists of many components including architectural components, operating system components, and application software components. The ability to represent and manipulate these components at high levels of abstraction is a major challenge. To address these challenges we have developed a set of principles. Important principles evolved are synergy of separation of concerns, reusability, flexibility, ease of use, and support for multiple levels of abstraction. 'Synergy of Separation of Concerns' helps in maintaining transparency during all instances in the development of the integrated environment. One application is transparent to another application and in turn to the system architecture. Also in the system architecture, each module is designed independent of other modules. Well defined interfaces enable this transparency and easier to integrate. This also enhances component reuse and overall design environment modularity. 'Ease of Use' allows the user to shorten the learning curve involved. In SHINE, 'Flexibility' is addressed via support for plug-and-play of components in the design environment. We provide results to show the implementation of these principles. SHINE provides a cost-effective mechanism to develop a system co-design infrastructure. This will lead to early system verification and performance estimation resulting in shorter time-to-market. The design flow developed is structured and is easily extended. This is an exploratory study that is the result of a long term industrial collaboration to enhance design productivity. Significantly more work lies ahead in developing an industry standard tool and methodology.
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Date Issued: 2003
PURL: http://purl.flvc.org/fau/fd/FADT12065
Subject Headings: Computer architecture, System design, Systems software, Multiprocessors
Format: Document (PDF)

FAU Theses and Dissertations (36)	+ -
Florida Atlantic University Patents (5)	+ -
FAU College Collections (2)	+ -
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Integrated circuits--Very large scale integration (6)	+ -
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Optical character recognition devices (4)	+ -
Optical character recognition devices--Computer simulation (4)	+ -

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Artificial intelligence (2)	+ -
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Pattern recognition systems (2)	+ -
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patent (5)	+ -
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Shankar, Ravi (44)	+ -
Florida Atlantic University (41)	+ -
College of Engineering and Computer Science (25)	+ -
Department of Computer and Electrical Engineering and Computer Science (24)	+ -
Esnard, Ann-Margaret (2)	+ -

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