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Highly scalable multiplier

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Date Issued:
2003
Summary:
High speed low power scalable multiplier is needed in computation intensive DSP applications such as video and image compression algorithms. We used an algorithm that folds the larger bit-width operands so smaller bit-width multipliers can be used. Successive folding on operands can be done until a desired threshold is reached. This method has inherent advantages of reuse of optimized building blocks, dynamic reconfiguration, and low power. We implemented a hardware multiplier based on this algorithm using Verilog hardware description language. Our results show that this multiplier exhibited significant power advantage over Array and Wallace Tree multipliers for comparable speeds, but had higher gate counts.
Title: Highly scalable multiplier.
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Name(s): Ajmera, Abhijit M.
Florida Atlantic University, Degree grantor
Shankar, Ravi, Thesis advisor
Type of Resource: text
Genre: Electronic Thesis Or Dissertation
Issuance: monographic
Date Issued: 2003
Publisher: Florida Atlantic University
Place of Publication: Boca Raton, Fla.
Physical Form: application/pdf
Extent: 96 p.
Language(s): English
Summary: High speed low power scalable multiplier is needed in computation intensive DSP applications such as video and image compression algorithms. We used an algorithm that folds the larger bit-width operands so smaller bit-width multipliers can be used. Successive folding on operands can be done until a desired threshold is reached. This method has inherent advantages of reuse of optimized building blocks, dynamic reconfiguration, and low power. We implemented a hardware multiplier based on this algorithm using Verilog hardware description language. Our results show that this multiplier exhibited significant power advantage over Array and Wallace Tree multipliers for comparable speeds, but had higher gate counts.
Identifier: 9780496219186 (isbn), 13080 (digitool), FADT13080 (IID), fau:9944 (fedora)
Collection: FAU Electronic Theses and Dissertations Collection
Note(s): College of Engineering and Computer Science
Thesis (M.S.)--Florida Atlantic University, 2003.
Subject(s): Digital multipliers--Design and construction
Multipliers (Mathematical analysis)
Verilog (Computer hardware description language)
Held by: Florida Atlantic University Libraries
Persistent Link to This Record: http://purl.flvc.org/fcla/dt/13080
Sublocation: Digital Library
Use and Reproduction: Copyright © is held by the author, with permission granted to Florida Atlantic University to digitize, archive and distribute this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder.
Use and Reproduction: http://rightsstatements.org/vocab/InC/1.0/
Host Institution: FAU
Is Part of Series: Florida Atlantic University Digital Library Collections.