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Survey of design techniques for signal integrity
- Date Issued:
- 2003
- Summary:
- Signal Integrity is a major bottleneck for DSM designs. Signal integrity refers to wide variety of problems, which leads to misconception. Signal integrity causes delay or noise at the high-level, but this boils down to resistance, capacitance and inductance (RLC) at circuit level. Several analysis and reduction techniques were proposed for reducing these effects on signal integrity. This work solves the misconception by encompassing different problems Chat effect signal integrity and can be good reference for a integrated circuit designer. The objective is to analyze these modeling methods, reduction techniques, tools and make recommendations that aids in developing a methodology for perfect design closure with an emphasis on signal integrity. These recommendations would form a basis for developing a methodology to analyze interference effects at higher levels of abstraction.
Title: | Survey of design techniques for signal integrity. |
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Name(s): |
Karnati, Raghuveer. Florida Atlantic University, Degree grantor Shankar, Ravi, Thesis advisor College of Engineering and Computer Science Department of Computer and Electrical Engineering and Computer Science |
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Type of Resource: | text | |
Genre: | Electronic Thesis Or Dissertation | |
Issuance: | monographic | |
Date Issued: | 2003 | |
Publisher: | Florida Atlantic University | |
Place of Publication: | Boca Raton, Fla. | |
Physical Form: | application/pdf | |
Extent: | 225 p. | |
Language(s): | English | |
Summary: | Signal Integrity is a major bottleneck for DSM designs. Signal integrity refers to wide variety of problems, which leads to misconception. Signal integrity causes delay or noise at the high-level, but this boils down to resistance, capacitance and inductance (RLC) at circuit level. Several analysis and reduction techniques were proposed for reducing these effects on signal integrity. This work solves the misconception by encompassing different problems Chat effect signal integrity and can be good reference for a integrated circuit designer. The objective is to analyze these modeling methods, reduction techniques, tools and make recommendations that aids in developing a methodology for perfect design closure with an emphasis on signal integrity. These recommendations would form a basis for developing a methodology to analyze interference effects at higher levels of abstraction. | |
Identifier: | 9780496219032 (isbn), 13065 (digitool), FADT13065 (IID), fau:9930 (fedora) | |
Collection: | FAU Electronic Theses and Dissertations Collection | |
Note(s): |
College of Engineering and Computer Science Thesis (M.S.)--Florida Atlantic University, 2003. |
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Subject(s): |
Integrated circuits--Design and construction Signal processing Electronic circuit design |
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Held by: | Florida Atlantic University Libraries | |
Persistent Link to This Record: | http://purl.flvc.org/fcla/dt/13065 | |
Sublocation: | Digital Library | |
Use and Reproduction: | Copyright © is held by the author, with permission granted to Florida Atlantic University to digitize, archive and distribute this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder. | |
Use and Reproduction: | http://rightsstatements.org/vocab/InC/1.0/ | |
Host Institution: | FAU | |
Is Part of Series: | Florida Atlantic University Digital Library Collections. |