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Modeling multiple abstraction levels in SoC using SystemC

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Date Issued:
2003
Summary:
Technological advances are providing us with the capability to integrate more and more functionality into a single chip. This is leading to a new design paradigm, System On a Chip (SoC). SoC design brings with it new challenges and difficulties. Managing these challenges and complexity necessitate modeling of systems at a hierarchy of abstraction levels starting from System Level down to Register Transfer Level. Using a single language across all these levels would ensure that the models are consistent and error-free. SystemC is one such language that has the infrastructure for specifying the design at System level, Behavioral level and RT levels of abstraction. This thesis showcases the same using two design examples---Simplex Data Protocol and General Purpose Timer (GPT) peripheral. Coding style and level of detailing at different levels are shows. Process of refining from one level to another is illustrated. GPT peripheral module designed in this thesis work can be further reused as a timer library component in system architectures.
Title: Modeling multiple abstraction levels in SoC using SystemC.
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Name(s): Jillellamudi, Haritha.
Florida Atlantic University, Degree grantor
Shankar, Ravi, Thesis advisor
Type of Resource: text
Genre: Electronic Thesis Or Dissertation
Issuance: monographic
Date Issued: 2003
Publisher: Florida Atlantic University
Place of Publication: Boca Raton, Fla.
Physical Form: application/pdf
Extent: 207 p.
Language(s): English
Summary: Technological advances are providing us with the capability to integrate more and more functionality into a single chip. This is leading to a new design paradigm, System On a Chip (SoC). SoC design brings with it new challenges and difficulties. Managing these challenges and complexity necessitate modeling of systems at a hierarchy of abstraction levels starting from System Level down to Register Transfer Level. Using a single language across all these levels would ensure that the models are consistent and error-free. SystemC is one such language that has the infrastructure for specifying the design at System level, Behavioral level and RT levels of abstraction. This thesis showcases the same using two design examples---Simplex Data Protocol and General Purpose Timer (GPT) peripheral. Coding style and level of detailing at different levels are shows. Process of refining from one level to another is illustrated. GPT peripheral module designed in this thesis work can be further reused as a timer library component in system architectures.
Identifier: 9780496219025 (isbn), 13064 (digitool), FADT13064 (IID), fau:9929 (fedora)
Collection: FAU Electronic Theses and Dissertations Collection
Note(s): College of Engineering and Computer Science
Thesis (M.S.)--Florida Atlantic University, 2003.
Subject(s): Systems on a chip
Abstraction
C++ (Computer program language)
System design
Held by: Florida Atlantic University Libraries
Persistent Link to This Record: http://purl.flvc.org/fcla/dt/13064
Sublocation: Digital Library
Use and Reproduction: Copyright © is held by the author, with permission granted to Florida Atlantic University to digitize, archive and distribute this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder.
Use and Reproduction: http://rightsstatements.org/vocab/InC/1.0/
Host Institution: FAU
Is Part of Series: Florida Atlantic University Digital Library Collections.