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DSP implementation of Turbo codes using the soft output Viterbi algorithm

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Date Issued:
1999
Summary:
There are various algorithms used for the iterative decoding of two-dimensional systematic convolutional codes in applications such as spread-spectrum communications and CDMA detection. The main objective of these decoding schemes is to approach the Shannon limit in signal-to-noise ratio while keeping the system complexity and processing delay to a minimum. One such scheme proposed recently is termed Turbo (de)coding. Through the use of Log-likelihood algebra, it is shown that a decoder can be developed which accepts soft inputs as a priori information and delivers soft outputs consisting of channel information, a priori information and extrinsic information to subsequent stages of iteration. The output is then used as the a priori input information for the next iteration. Realization of the Turbo decoder is performed on the digital signal processing chip, TMS320C30 by Texas Instruments using a low complexity soft-input soft-output decoding algorithm. Hardware issues such as memory and processing time are addressed and how they are impacted by the chosen decoding scheme. Test results of the BER performance are presented for various block sizes and number of iterations.
Title: DSP implementation of Turbo codes using the soft output Viterbi algorithm.
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Name(s): Dewsnap, Robert C.
Florida Atlantic University, Degree grantor
Sudhakar, Raghavan, Thesis advisor
College of Engineering and Computer Science
Department of Computer and Electrical Engineering and Computer Science
Type of Resource: text
Genre: Electronic Thesis Or Dissertation
Issuance: monographic
Date Issued: 1999
Publisher: Florida Atlantic University
Place of Publication: Boca Raton, Fla.
Physical Form: application/pdf
Extent: 98 p.
Language(s): English
Summary: There are various algorithms used for the iterative decoding of two-dimensional systematic convolutional codes in applications such as spread-spectrum communications and CDMA detection. The main objective of these decoding schemes is to approach the Shannon limit in signal-to-noise ratio while keeping the system complexity and processing delay to a minimum. One such scheme proposed recently is termed Turbo (de)coding. Through the use of Log-likelihood algebra, it is shown that a decoder can be developed which accepts soft inputs as a priori information and delivers soft outputs consisting of channel information, a priori information and extrinsic information to subsequent stages of iteration. The output is then used as the a priori input information for the next iteration. Realization of the Turbo decoder is performed on the digital signal processing chip, TMS320C30 by Texas Instruments using a low complexity soft-input soft-output decoding algorithm. Hardware issues such as memory and processing time are addressed and how they are impacted by the chosen decoding scheme. Test results of the BER performance are presented for various block sizes and number of iterations.
Identifier: 9780599201279 (isbn), 15616 (digitool), FADT15616 (IID), fau:12373 (fedora)
Collection: FAU Electronic Theses and Dissertations Collection
Note(s): College of Engineering and Computer Science
Thesis (M.S.E.E.)--Florida Atlantic University, 1999.
Subject(s): Engineering, Electronics and Electrical
Held by: Florida Atlantic University Libraries
Persistent Link to This Record: http://purl.flvc.org/fcla/dt/15616
Sublocation: Digital Library
Use and Reproduction: Copyright © is held by the author, with permission granted to Florida Atlantic University to digitize, archive and distribute this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder.
Use and Reproduction: http://rightsstatements.org/vocab/InC/1.0/
Host Institution: FAU
Is Part of Series: Florida Atlantic University Digital Library Collections.