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Design of analog building blocks useful for artificial neural networks

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Date Issued:
1996
Summary:
Software simulations of a scaleable VLSI implementable architecture and algorithm for character recognition by a research group at Florida Atlantic University (FAU) have shown encouraging results. We address here hardware implementation issues pertinent to the classification phase of character recognition. Using the digit classification techniques developed at FAU as a foundation, we have designed and simulated general purpose building blocks useful for a possible implementation of a Digital & Analog CMOS VLSI chip that is suitable for a variety of artificial neural network (ANN) architectures. HSPICE was used to perform circuit-level simulations of the building blocks. We present here the details of implementation of the recognition chip including the architecture, circuit design and the simulation results.
Title: Design of analog building blocks useful for artificial neural networks.
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Name(s): Renavikar, Ajit Anand.
Florida Atlantic University, Degree grantor
Shankar, Ravi, Thesis advisor
College of Engineering and Computer Science
Department of Computer and Electrical Engineering and Computer Science
Type of Resource: text
Genre: Electronic Thesis Or Dissertation
Issuance: monographic
Date Issued: 1996
Publisher: Florida Atlantic University
Place of Publication: Boca Raton, Fla.
Physical Form: application/pdf
Extent: 151 p.
Language(s): English
Summary: Software simulations of a scaleable VLSI implementable architecture and algorithm for character recognition by a research group at Florida Atlantic University (FAU) have shown encouraging results. We address here hardware implementation issues pertinent to the classification phase of character recognition. Using the digit classification techniques developed at FAU as a foundation, we have designed and simulated general purpose building blocks useful for a possible implementation of a Digital & Analog CMOS VLSI chip that is suitable for a variety of artificial neural network (ANN) architectures. HSPICE was used to perform circuit-level simulations of the building blocks. We present here the details of implementation of the recognition chip including the architecture, circuit design and the simulation results.
Identifier: 15328 (digitool), FADT15328 (IID), fau:12097 (fedora)
Collection: FAU Electronic Theses and Dissertations Collection
Note(s): College of Engineering and Computer Science
Thesis (M.S.)--Florida Atlantic University, 1996.
Subject(s): Neural networks (Computer science)
Artificial intelligence
Optical character recognition devices
Pattern recognition systems
Held by: Florida Atlantic University Libraries
Persistent Link to This Record: http://purl.flvc.org/fcla/dt/15328
Sublocation: Digital Library
Use and Reproduction: Copyright © is held by the author, with permission granted to Florida Atlantic University to digitize, archive and distribute this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder.
Use and Reproduction: http://rightsstatements.org/vocab/InC/1.0/
Host Institution: FAU
Is Part of Series: Florida Atlantic University Digital Library Collections.