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System level simulations of an optical character recognition system
- Date Issued:
- 1994
- Summary:
- Optical Character Recognition systems have many applications in today's world of electronic computing. Various software implementations are currently being used. This thesis evolves a massively parallel hardware implementation for the system that is VLSI scaleable and may lead to substantial increase in the processing speed. This system involves various stages for preprocessing and processing of the image implemented with SIMD architecture, using simple processing elements and near neighbor communications. The architecture evolved is simulated using the Verilog Hardware Description Language. This project should provide a framework for a massively parallel processing architecture for such systems. It is expected that this project will lead to the design and implementation of a real time system.
Title: | System level simulations of an optical character recognition system. |
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Name(s): |
Phadnis, Mangirish Jayawant. Florida Atlantic University, Degree grantor Shankar, Ravi, Thesis advisor College of Engineering and Computer Science Department of Computer and Electrical Engineering and Computer Science |
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Type of Resource: | text | |
Genre: | Electronic Thesis Or Dissertation | |
Issuance: | monographic | |
Date Issued: | 1994 | |
Publisher: | Florida Atlantic University | |
Place of Publication: | Boca Raton, Fla. | |
Physical Form: | application/pdf | |
Extent: | 97 p. | |
Language(s): | English | |
Summary: | Optical Character Recognition systems have many applications in today's world of electronic computing. Various software implementations are currently being used. This thesis evolves a massively parallel hardware implementation for the system that is VLSI scaleable and may lead to substantial increase in the processing speed. This system involves various stages for preprocessing and processing of the image implemented with SIMD architecture, using simple processing elements and near neighbor communications. The architecture evolved is simulated using the Verilog Hardware Description Language. This project should provide a framework for a massively parallel processing architecture for such systems. It is expected that this project will lead to the design and implementation of a real time system. | |
Identifier: | 15106 (digitool), FADT15106 (IID), fau:11883 (fedora) | |
Collection: | FAU Electronic Theses and Dissertations Collection | |
Note(s): |
College of Engineering and Computer Science Thesis (M.S.C.E.)--Florida Atlantic University, 1994. |
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Subject(s): |
Optical character recognition devices Integrated circuits--Very large scale integration Optical scanners Image processing--Digital techniques |
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Held by: | Florida Atlantic University Libraries | |
Persistent Link to This Record: | http://purl.flvc.org/fcla/dt/15106 | |
Sublocation: | Digital Library | |
Use and Reproduction: | Copyright © is held by the author, with permission granted to Florida Atlantic University to digitize, archive and distribute this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder. | |
Use and Reproduction: | http://rightsstatements.org/vocab/InC/1.0/ | |
Host Institution: | FAU | |
Is Part of Series: | Florida Atlantic University Digital Library Collections. |