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Digital implementation of Alopex: HDL simulation studies

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Date Issued:
1990
Summary:
Alopex is a stochastic algorithm used to solve optimization problems in various types of systems. This thesis describes behavioral and structural hardware-description-language models which were developed for a three-stage VLSI-implementable Alopex architecture. The architecture features an SIMD structure and no communication between processing elements (PEs). Several approximations and simplifications were tested using the models to achieve a simple PE architecture and to implement the algorithm using integer arithmetic. Simulations were conducted with numerical image input to check the validity of these changes, and the timing relationships between PEs and controllers were explored. The use of a hardware description language provided an easy way to investigate timing and make architectural changes. The algorithm was found to function correctly under the digital hardware constraints and simplifications. The timing results gave an indication of the execution time for each step and pointed out areas in which the architecture may need to be improved.
Title: Digital implementation of Alopex: HDL simulation studies.
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Name(s): Freytag, Lynn R.
Florida Atlantic University, Degree grantor
Shankar, Ravi, Thesis advisor
Type of Resource: text
Genre: Electronic Thesis Or Dissertation
Issuance: monographic
Date Issued: 1990
Publisher: Florida Atlantic University
Place of Publication: Boca Raton, Fla.
Physical Form: application/pdf
Extent: 281 p.
Language(s): English
Summary: Alopex is a stochastic algorithm used to solve optimization problems in various types of systems. This thesis describes behavioral and structural hardware-description-language models which were developed for a three-stage VLSI-implementable Alopex architecture. The architecture features an SIMD structure and no communication between processing elements (PEs). Several approximations and simplifications were tested using the models to achieve a simple PE architecture and to implement the algorithm using integer arithmetic. Simulations were conducted with numerical image input to check the validity of these changes, and the timing relationships between PEs and controllers were explored. The use of a hardware description language provided an easy way to investigate timing and make architectural changes. The algorithm was found to function correctly under the digital hardware constraints and simplifications. The timing results gave an indication of the execution time for each step and pointed out areas in which the architecture may need to be improved.
Identifier: 14650 (digitool), FADT14650 (IID), fau:11443 (fedora)
Collection: FAU Electronic Theses and Dissertations Collection
Note(s): College of Engineering and Computer Science
Thesis (M.S.C.E.)--Florida Atlantic University, 1990.
Subject(s): Computer hardware description languages--Simulation methods
Held by: Florida Atlantic University Libraries
Persistent Link to This Record: http://purl.flvc.org/fcla/dt/14650
Sublocation: Digital Library
Use and Reproduction: Copyright © is held by the author, with permission granted to Florida Atlantic University to digitize, archive and distribute this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder.
Use and Reproduction: http://rightsstatements.org/vocab/InC/1.0/
Host Institution: FAU
Is Part of Series: Florida Atlantic University Digital Library Collections.