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DIGITAL PCM MF RECEIVER

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Date Issued:
1987
Summary:
A PCM MF Receiver based on either analog or digital filters results in a fairly large chip. A recent publication attempts to address this issue by using certain approximations that replace multiplications with simple additions and subtractions. This results in a significantly smaller chip. In our research, we have further refined/changed the algorithms and approximations in order to reduce the chip size further and the chip count to one. A simulation model corresponding to this, written in ISPS and Fortran, was extensively utilized to verify that the proposed receiver would meet and/or exceed all the commercial specifications. Subsequent to that, we initiated hardware design using structured methodologies. Hardware modules written in a high-level hardware description language have been simulated for functional validity. We expect to utilize mixed mode simulations and hierarchical design concepts in translating this high-level description to a hardware implementation on a semi-custom CMOS chip.
Title: DIGITAL PCM MF RECEIVER.
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Name(s): CHENTHANAKIJ, APICHAI.
Florida Atlantic University, Degree grantor
Shankar, Ravi, Thesis advisor
Type of Resource: text
Genre: Electronic Thesis Or Dissertation
Issuance: monographic
Date Issued: 1987
Publisher: Florida Atlantic University
Place of Publication: Boca Raton, Fla.
Physical Form: application/pdf
Extent: 146 p.
Language(s): English
Summary: A PCM MF Receiver based on either analog or digital filters results in a fairly large chip. A recent publication attempts to address this issue by using certain approximations that replace multiplications with simple additions and subtractions. This results in a significantly smaller chip. In our research, we have further refined/changed the algorithms and approximations in order to reduce the chip size further and the chip count to one. A simulation model corresponding to this, written in ISPS and Fortran, was extensively utilized to verify that the proposed receiver would meet and/or exceed all the commercial specifications. Subsequent to that, we initiated hardware design using structured methodologies. Hardware modules written in a high-level hardware description language have been simulated for functional validity. We expect to utilize mixed mode simulations and hierarchical design concepts in translating this high-level description to a hardware implementation on a semi-custom CMOS chip.
Identifier: 14354 (digitool), FADT14354 (IID), fau:11158 (fedora)
Collection: FAU Electronic Theses and Dissertations Collection
Note(s): College of Engineering and Computer Science
Thesis (M.S.E.)--Florida Atlantic University, 1987.
Subject(s): Electric filters, Digital--Computer programs
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Held by: Florida Atlantic University Libraries
Persistent Link to This Record: http://purl.flvc.org/fcla/dt/14354
Sublocation: Digital Library
Use and Reproduction: Copyright © is held by the author, with permission granted to Florida Atlantic University to digitize, archive and distribute this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder.
Use and Reproduction: http://rightsstatements.org/vocab/InC/1.0/
Host Institution: FAU
Is Part of Series: Florida Atlantic University Digital Library Collections.