You are here
SEMI-CUSTOM DESIGN OF A MICROPROGRAMMED TESTABLE REDUCED INSTRUCTION SET COMPUTER
- Date Issued:
- 1986
- Summary:
- The concept of a Reduced Instruction Set Computer (RISC) has evolved out of a desire to enhance the performance of a computer. We present here a detailed design of a Testable Reduced Instruction Set Computer (TRISC) that utilizes a Multiple Register Set. Level Sensitive Scan Design (LSSD) is used to incorporate testability into our design. We first evolved a functional description of the design using Digital Design Language (DDL) a hardware programming language. We then entered the schematic of the design into Daisy's Logician V, a CAD/CAE workstation, using NCR CMOSII Digital Standard Cell Library. We then performed a unit delay simulation on the hierarchical design database to ascertain the logical functioning of the system.
Title: | SEMI-CUSTOM DESIGN OF A MICROPROGRAMMED TESTABLE REDUCED INSTRUCTION SET COMPUTER. |
![]() ![]() |
---|---|---|
Name(s): |
POENATEETAI, VIWAT. Florida Atlantic University, Degree grantor Shankar, Ravi, Thesis advisor College of Engineering and Computer Science Department of Computer and Electrical Engineering and Computer Science |
|
Type of Resource: | text | |
Genre: | Electronic Thesis Or Dissertation | |
Issuance: | monographic | |
Date Issued: | 1986 | |
Publisher: | Florida Atlantic University | |
Place of Publication: | Boca Raton, Fla. | |
Physical Form: | application/pdf | |
Extent: | 195 p. | |
Language(s): | English | |
Summary: | The concept of a Reduced Instruction Set Computer (RISC) has evolved out of a desire to enhance the performance of a computer. We present here a detailed design of a Testable Reduced Instruction Set Computer (TRISC) that utilizes a Multiple Register Set. Level Sensitive Scan Design (LSSD) is used to incorporate testability into our design. We first evolved a functional description of the design using Digital Design Language (DDL) a hardware programming language. We then entered the schematic of the design into Daisy's Logician V, a CAD/CAE workstation, using NCR CMOSII Digital Standard Cell Library. We then performed a unit delay simulation on the hierarchical design database to ascertain the logical functioning of the system. | |
Identifier: | 14284 (digitool), FADT14284 (IID), fau:11092 (fedora) | |
Collection: | FAU Electronic Theses and Dissertations Collection | |
Note(s): |
Source: Masters Abstracts International, Volume: 24-03, page: 0291. College of Engineering and Computer Science |
|
Subject(s): |
Computer architecture Integrated circuits--Very large scale integration |
|
Held by: | Florida Atlantic University Libraries | |
Persistent Link to This Record: | http://purl.flvc.org/fcla/dt/14284 | |
Sublocation: | Digital Library | |
Use and Reproduction: | Copyright © is held by the author, with permission granted to Florida Atlantic University to digitize, archive and distribute this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder. | |
Use and Reproduction: | http://rightsstatements.org/vocab/InC/1.0/ | |
Host Institution: | FAU | |
Is Part of Series: | Florida Atlantic University Digital Library Collections. |