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Title: A very high-performance neural network system architecture using grouped weight quantization.
Creator: Karaali, Orhan., Florida Atlantic University, Shankar, Ravi, Gluch, David P., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Recently, Artificial Neural Network (ANN) computing systems have become one of the most active and challenging areas of information processing. The successes of experimental neural computing systems in the fields of pattern recognition, process control, robotics, signal processing, expert system, and functional analysis are most promising. However due to a number of serious problems, only small size fully connected neural networks have been implemented to run in real-time. The primary problem...
Show moreRecently, Artificial Neural Network (ANN) computing systems have become one of the most active and challenging areas of information processing. The successes of experimental neural computing systems in the fields of pattern recognition, process control, robotics, signal processing, expert system, and functional analysis are most promising. However due to a number of serious problems, only small size fully connected neural networks have been implemented to run in real-time. The primary problem is that the execution time of neural networks increases exponentially as the neural network's size increases. This is because of the exponential increase in the number of multiplications and interconnections which makes it extremely difficult to implement medium or large scale ANNs in hardware. The Modular Grouped Weight Quantization (MGWQ) presented in this dissertation is an ANN design which assures that the number of multiplications and interconnections increase linearly as the neural network's size increases. The secondary problems are related to scale-up capability, modularity, memory requirements, flexibility, performance, fault tolerance, technological feasibility, and cost. The MGWQ architecture also resolves these problems. In this dissertation, neural network characteristics and existing implementations using different technologies are described. Their shortcomings and problems are addressed, and solutions to these problems using the MGWQ approach are illustrated. The theoretical and experimental justifications for MGWQ are presented. Performance calculations for the MGWQ architecture are given. The mappings of the most popular neural network models to the proposed architecture are demonstrated. System level architecture considerations are discussed. The proposed ANN computing system is a flexible and a realistic way to implement large fully connected networks. It offers very high performance using currently available technology. The performance of ANNs is measured in terms of interconnections per second (IC/S); the performance of the proposed system changes between 10^11 to 10^14 IC/S. In comparison, SAIC's DELTA II ANN system achieves 10^7. A Cray X-MP achieves 5*10^7 IC/S.
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Date Issued: 1989
PURL: http://purl.flvc.org/fcla/dt/12245
Subject Headings: Neural circuitry, Neural computers, Computer architecture
Format: Document (PDF)

Title: Unifying the conceptual levels of network security through the use of patterns.
Creator: Kumar, Ajoy, Fernandez, Eduardo B., Florida Atlantic University, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Network architectures are described by the International Standard for Organization (ISO), which contains seven layers. The internet uses four of these layers, of which three are of interest to us. These layers are Internet Protocol (IP) or Network Layer, Transport Layer and Application Layer. We need to protect against attacks that may come through any of these layers. In the world of network security, systems are plagued by various attacks, internal and external, and could result in Denial...
Show moreNetwork architectures are described by the International Standard for Organization (ISO), which contains seven layers. The internet uses four of these layers, of which three are of interest to us. These layers are Internet Protocol (IP) or Network Layer, Transport Layer and Application Layer. We need to protect against attacks that may come through any of these layers. In the world of network security, systems are plagued by various attacks, internal and external, and could result in Denial of Service (DoS) and/or other damaging effects. Such attacks and loss of service can be devastating for the users of the system. The implementation of security devices such as Firewalls and Intrusion Detection Systems (IDS), the protection of network traffic with Virtual Private Networks (VPNs), and the use of secure protocols for the layers are important to enhance the security at each of these layers.We have done a survey of the existing network security patterns and we have written the missing patterns. We have developed security patterns for abstract IDS, Behavior–based IDS and Rule-based IDS and as well as for Internet Protocol Security (IPSec) and Transport Layer Security (TLS) protocols. We have also identified the need for a VPN pattern and have developed security patterns for abstract VPN, an IPSec VPN and a TLS VPN. We also evaluated these patterns with respect to some aspects to simplify their application by system designers. We have tried to unify the security of the network layers using security patterns by tying in security patterns for network transmission, network protocols and network boundary devices.
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Date Issued: 2014
PURL: http://purl.flvc.org/fau/fd/FA00004132, http://purl.flvc.org/fau/fd/FA00004132
Subject Headings: Computer architecture, Computer network architectures, Computer network protocols, Computer network protocols, Computer networks -- Security measures, Expert systems (Computer science)
Format: Document (PDF)

Title: A unified methodology for software and hardware fault tolerance.
Creator: Wang, Yijun., Florida Atlantic University, Wu, Jie, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: The growing demand for high availability of computer systems has led to a wide application range of fault-tolerant systems. In some real-time applications ultrareliable computer systems are required. Such computer systems should be capable of tolerating failures of not only their hardware components but also of their software components. This dissertation discusses three aspects of designing an ultrareliable system: (a) a hierarchical ultrareliable system structure; (b) a set of unified...
Show moreThe growing demand for high availability of computer systems has led to a wide application range of fault-tolerant systems. In some real-time applications ultrareliable computer systems are required. Such computer systems should be capable of tolerating failures of not only their hardware components but also of their software components. This dissertation discusses three aspects of designing an ultrareliable system: (a) a hierarchical ultrareliable system structure; (b) a set of unified methods to tolerate both software and hardware faults in combination; and (c) formal specifications in the system structure. The proposed hierarchical structure has four layers: Application, Software Fault Tolerance, Combined Fault Tolerance and Configuration. The Application Layer defines the structure of the application software in terms of the modular structure using a module interconnection language. The failure semantics of the service provided by the system is also defined at this layer. At the Software Fault Tolerance Layer each module can use software fault tolerance methods. The implementation of the software and hardware fault tolerance is achieved at the Combined Fault Tolerance Layer which utilizes the combined software/hardware fault tolerance methods. The Configuration Layer performs actual software and hardware resource management for the requests of fault identification and recovery from the Combined Fault Tolerance Layer. A combined software and hardware fault model is used as the system fault model. This model uses the concepts of fault pattern and fault set to abstract the various occurrences of software and hardware faults. We also discuss extended comparison models that consider faulty software as well. The combined software/hardware fault tolerance methods are based on recovery blocks, N-version programming, extended comparison methods and both forward and backward recovery methods. Formal specifications and verifications are used in the system design process and the system structure to show that the design and implementation of a fault-tolerant system satisfy the functional and non-functional requirements. Brief discussions and examples of using formal specifications in the hierarchical structure are given.
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Date Issued: 1995
PURL: http://purl.flvc.org/fcla/dt/12424
Subject Headings: Fault-tolerant computing, Computer architecture
Format: Document (PDF)

Title: Time-step optimal broadcasting in mesh networks with minimum total communication distance.
Creator: Cang, Songluan., Florida Atlantic University, Wu, Jie
Abstract/Description: We propose a new minimum total communication distance (TCD) algorithm and an optimal TCD algorithm for broadcast in a 2-dimensional mesh (2-D mesh). The former generates a minimum TCD from a given source node, and the latter guarantees a minimum TCD among all the possible source nodes. These algorithms are based on a divide-and-conquer approach where a 2-D mesh is partitioned into four submeshes of equal size. The source node sends the broadcast message to a special node called an eye in each...
Show moreWe propose a new minimum total communication distance (TCD) algorithm and an optimal TCD algorithm for broadcast in a 2-dimensional mesh (2-D mesh). The former generates a minimum TCD from a given source node, and the latter guarantees a minimum TCD among all the possible source nodes. These algorithms are based on a divide-and-conquer approach where a 2-D mesh is partitioned into four submeshes of equal size. The source node sends the broadcast message to a special node called an eye in each submesh. The above procedure is then recursively applied in each submesh. These algorithms are extended to a 3-dimensional mesh (3-D mesh), and are generalized to a d-dimensional mesh or torus. In addition, the proposed approach can potentially be used to solve optimization problems in other collective communication operations.
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Date Issued: 1999
PURL: http://purl.flvc.org/fcla/dt/15647
Subject Headings: Computer algorithms, Parallel processing (Electronic computers), Computer architecture
Format: Document (PDF)

Title: Software decomposition for multicore architectures.
Creator: Jain, Ankit., Florida Atlantic University, Shankar, Ravi
Abstract/Description: Current multicore processors attempt to optimize consumer experience via task partitioning and concurrent execution of these (sub)tasks on the cores. Conversion of sequential code to parallel and concurrent code is neither easy, nor feasible with current methodologies. We have developed a mapping process that synergistically uses top-down and bottom-up methodologies. This process is amenable to automation. We use bottom-up analysis to determine decomposability and estimate computation and...
Show moreCurrent multicore processors attempt to optimize consumer experience via task partitioning and concurrent execution of these (sub)tasks on the cores. Conversion of sequential code to parallel and concurrent code is neither easy, nor feasible with current methodologies. We have developed a mapping process that synergistically uses top-down and bottom-up methodologies. This process is amenable to automation. We use bottom-up analysis to determine decomposability and estimate computation and communication metrics. The outcome is a set of proposals for software decomposition. We then build abstract concurrent models that map these decomposed (abstract) software modules onto candidate multicore architectures; this resolves concurrency issues. We then perform a system level simulation to estimate concurrency gain and/or cost, and QOS (Qualify-of-Service) metrics. Different architectural combinations yield different QOS metrics; the requisite system architecture may then be chosen. We applied this 'middle-out' methodology to optimally map a digital camera application onto a processor with four cores.
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Date Issued: 2006
PURL: http://purl.flvc.org/fcla/dt/13349
Subject Headings: Optimal designs (Statistics), Software architecture, Software engineering, Computer architecture, System design, Computer networks--Security measures
Format: Document (PDF)

Title: Simulation analysis of cluster-based multiprocessor systems.
Creator: De Armas, Mario Ernesto., Florida Atlantic University, Mahgoub, Imad
Abstract/Description: Multiprocessor systems have demonstrated great potential for meeting the ever increasing demand for higher performance. In this thesis, we develop simulation models with fewer and more realistic assumptions to evaluate the performance of the circuit-switched cluster-based multiprocessor system. We then introduce a packet-switched variation of the cluster-based architecture and develop simulation models to evaluate its performance. The analysis of the cluster-based systems is performed for...
Show moreMultiprocessor systems have demonstrated great potential for meeting the ever increasing demand for higher performance. In this thesis, we develop simulation models with fewer and more realistic assumptions to evaluate the performance of the circuit-switched cluster-based multiprocessor system. We then introduce a packet-switched variation of the cluster-based architecture and develop simulation models to evaluate its performance. The analysis of the cluster-based systems is performed for both uniform and non-uniform memory reference models. We conducted similar analysis for the crossbar and multiple-bus systems. Finally, the results of the cluster-based systems are compared to those obtained for the crossbar and the multiple-bus systems.
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Date Issued: 1993
PURL: http://purl.flvc.org/fcla/dt/14969
Subject Headings: Multiprocessors, Cluster analysis, Packet switching (Data transmission), Computer architecture, Computer simulation
Format: Document (PDF)

Title: SHINE: An integrated environment for software hardware co-design.
Creator: Jayadevappa, Suryaprasad., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: The rapid evolution of silicon technology has brought exponential benefits in cost, scale of integration, power per function, size per function and speed. The ability to place multiple function "systems" on a single silicon chip, reduce development cycle while increasing product functionality, performance and quality. With this increased complexity, ability to model at high level of abstraction becomes crucial. Also, the fact that no known existing complete system on chip design packages with...
Show moreThe rapid evolution of silicon technology has brought exponential benefits in cost, scale of integration, power per function, size per function and speed. The ability to place multiple function "systems" on a single silicon chip, reduce development cycle while increasing product functionality, performance and quality. With this increased complexity, ability to model at high level of abstraction becomes crucial. Also, the fact that no known existing complete system on chip design packages with perfect tools, models, and formalisms further slows down and complicates the development. This dissertation provides an integrated environment for hardware software co-design at a high level of abstraction. We have developed a SystemC based cockpit for this purpose. The cockpit, known as SHINE consists of many components including architectural components, operating system components, and application software components. The ability to represent and manipulate these components at high levels of abstraction is a major challenge. To address these challenges we have developed a set of principles. Important principles evolved are synergy of separation of concerns, reusability, flexibility, ease of use, and support for multiple levels of abstraction. 'Synergy of Separation of Concerns' helps in maintaining transparency during all instances in the development of the integrated environment. One application is transparent to another application and in turn to the system architecture. Also in the system architecture, each module is designed independent of other modules. Well defined interfaces enable this transparency and easier to integrate. This also enhances component reuse and overall design environment modularity. 'Ease of Use' allows the user to shorten the learning curve involved. In SHINE, 'Flexibility' is addressed via support for plug-and-play of components in the design environment. We provide results to show the implementation of these principles. SHINE provides a cost-effective mechanism to develop a system co-design infrastructure. This will lead to early system verification and performance estimation resulting in shorter time-to-market. The design flow developed is structured and is easily extended. This is an exploratory study that is the result of a long term industrial collaboration to enhance design productivity. Significantly more work lies ahead in developing an industry standard tool and methodology.
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Date Issued: 2003
PURL: http://purl.flvc.org/fau/fd/FADT12065
Subject Headings: Computer architecture, System design, Systems software, Multiprocessors
Format: Document (PDF)

Title: SEMI-CUSTOM DESIGN OF A MICROPROGRAMMED TESTABLE REDUCED INSTRUCTION SET COMPUTER.
Creator: POENATEETAI, VIWAT., Florida Atlantic University, Shankar, Ravi, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: The concept of a Reduced Instruction Set Computer (RISC) has evolved out of a desire to enhance the performance of a computer. We present here a detailed design of a Testable Reduced Instruction Set Computer (TRISC) that utilizes a Multiple Register Set. Level Sensitive Scan Design (LSSD) is used to incorporate testability into our design. We first evolved a functional description of the design using Digital Design Language (DDL) a hardware programming language. We then entered the schematic...
Show moreThe concept of a Reduced Instruction Set Computer (RISC) has evolved out of a desire to enhance the performance of a computer. We present here a detailed design of a Testable Reduced Instruction Set Computer (TRISC) that utilizes a Multiple Register Set. Level Sensitive Scan Design (LSSD) is used to incorporate testability into our design. We first evolved a functional description of the design using Digital Design Language (DDL) a hardware programming language. We then entered the schematic of the design into Daisy's Logician V, a CAD/CAE workstation, using NCR CMOSII Digital Standard Cell Library. We then performed a unit delay simulation on the hierarchical design database to ascertain the logical functioning of the system.
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Date Issued: 1986
PURL: http://purl.flvc.org/fcla/dt/14284
Subject Headings: Computer architecture, Integrated circuits--Very large scale integration
Format: Document (PDF)

Title: Processor allocation in hypercube computers.
Creator: Sua, Jose Reinier., Florida Atlantic University, Mahgoub, Imad, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: In this thesis, processor allocation in hypercube computers is viewed to consist of the following three components. The ability to have complete subcube recognition, the heuristics and methods to speedup the recognition of free subcubes, and the policy to schedule incoming tasks to reduce the fragmentation of the hypercube. We propose a fast processor allocation strategy for hypercube computers called modified gray code (MGC). The MGC strategy achieves full subcube recognition with much less...
Show moreIn this thesis, processor allocation in hypercube computers is viewed to consist of the following three components. The ability to have complete subcube recognition, the heuristics and methods to speedup the recognition of free subcubes, and the policy to schedule incoming tasks to reduce the fragmentation of the hypercube. We propose a fast processor allocation strategy for hypercube computers called modified gray code (MGC). The MGC strategy achieves full subcube recognition with much less complexity than the multiple gray code and the tree collapse strategies. It is the first bitmapped strategy to incorporate binary search and heuristics to locate free subcubes, and has a new scheduling policy which significantly reduces the fragmentation of the hypercube. Simulation programs have been developed to compare the performance of the MGC to that of the other strategies so as to demonstrate its effectiveness. Results obtained showed that, in most of the situations, the MGC outperformed the other strategies, especially when the system load is high. We have also investigated processor allocation methods for real-time systems with fault-tolerant considerations. We propose methods that can handle a minimum of two dynamically occurring faults, without slowdown in execution and with a constant slowdown in communication of 3.
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Date Issued: 1993
PURL: http://purl.flvc.org/fcla/dt/14904
Subject Headings: Hypercube networks (Computer networks), Computer architecture, Real-time data processing
Format: Document (PDF)

Title: PERFORMANCE EVALUATION OF A RIDGE 32 COMPUTER SYSTEM (RISC (REDUCED INSTRUCTION SET COMPUTER)).
Creator: YOON, SEOK TAE., Florida Atlantic University, Fernandez, Eduardo B., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: As a new trend in designing a computer architecture, Reduced Instruction set Computers(RISC) have been proposed recently. This thesis reviews the new design approach behind the RISC and discuss the controversy between the proponents of the RISC approach and those of the traditional Complex Instruction set COmputer(CISC) approach. Ridge 32 is selected as a case study of the RISCs. Architectural parameters to evaluate the computer performance are considered to analyze the performance of the...
Show moreAs a new trend in designing a computer architecture, Reduced Instruction set Computers(RISC) have been proposed recently. This thesis reviews the new design approach behind the RISC and discuss the controversy between the proponents of the RISC approach and those of the traditional Complex Instruction set COmputer(CISC) approach. Ridge 32 is selected as a case study of the RISCs. Architectural parameters to evaluate the computer performance are considered to analyze the performance of the Ridge 32. A simulator for the Ridge 32 was implemented in PASCAL as a way of measuring those parameters. Measurement results on the several selected benchmark programs are given and analyzed to evaluate the characteristics of the Ridge 32.
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Date Issued: 1986
PURL: http://purl.flvc.org/fcla/dt/14348
Subject Headings: Computer architecture, Microprocessors
Format: Document (PDF)

Title: An integrated component selection framework for system level design.
Creator: Calvert, Chad., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: The increasing system design complexity is negatively impacting the overall system design productivity by increasing the cost and time of product development. One key to overcoming these challenges is exploiting Component Based Engineering practices. However it is a challenge to select an optimum component from a component library that will satisfy all system functional and non-functional requirements, due to varying performance parameters and quality of service requirements. In this thesis...
Show moreThe increasing system design complexity is negatively impacting the overall system design productivity by increasing the cost and time of product development. One key to overcoming these challenges is exploiting Component Based Engineering practices. However it is a challenge to select an optimum component from a component library that will satisfy all system functional and non-functional requirements, due to varying performance parameters and quality of service requirements. In this thesis we propose an integrated framework for component selection. The framework is a two phase approach that includes a system modeling and analysis phase and a component selection phase. Three component selection algorithms have been implemented for selecting components for a Network on Chip architecture. Two algorithms are based on a standard greedy method, with one being enhanced to produce more intelligent behavior. The third algorithm is based on simulated annealing. Further, a prototype was developed to evaluate the proposed framework and compare the performance of all the algorithms.
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Date Issued: 2009
PURL: http://purl.flvc.org/FAU/368608
Subject Headings: High performance computing, Computer architecture, Engineering design, Data processing, Computer-aided design
Format: Document (PDF)

Title: A high-speed switching node architecture for ATM networks.
Creator: Syed, Majid Ali, Florida Atlantic University, Ilyas, Mohammad, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: This research is aimed towards the concept of a new switching node architecture for cell-switched Asynchronous Transfer Mode (ATM) networks. The proposed architecture has several distinguishing features when compared with existing Banyan based switching node. It has a cylindrical structure as opposed to a flat structure as found in Banyans. The wrap around property results in better link utilization as compared with existing Banyans beside resulting in reduced average route length. Simplified...
Show moreThis research is aimed towards the concept of a new switching node architecture for cell-switched Asynchronous Transfer Mode (ATM) networks. The proposed architecture has several distinguishing features when compared with existing Banyan based switching node. It has a cylindrical structure as opposed to a flat structure as found in Banyans. The wrap around property results in better link utilization as compared with existing Banyans beside resulting in reduced average route length. Simplified digit controlled routing is maintained as found in Banyans. The cylindrical nature of the architecture, results in pipeline activity. Such architecture tends to sort the traffic to a higher address, eliminating the need of a preprocessing node as a front end processing node. Approximate Markov chain analyses for the performance of the switching node with single input buffers is presented. The analyses are used to compute the time delay distribution of a cell leaving the node. A simulation tool is used to validate the analytical model. The simulation model is free from the critical assumptions which are necessary to develop the analytical model. It is shown that the analytical results closely match with the simulation results. This confirms the authenticity of the simulation model. We then study the performance of the switching node for various input buffer sizes. Low throughput with single input buffered switching node is observed; however, as the buffer size is increased from two to three the increase in throughput is more than 100%. No appreciable increase in node delay is noted when the buffer size is increased from two to three. We conclude that the optimum buffer size for large throughput is three and the maximum throughput with offered load of 0.9 and buffer size three is 0.75. This is because of head of line blocking phenomenon. A technique to overcome such inherent problem is presented. Several delays which a cell faces are analyzed and summarized below. The wait delay with buffer sizes one and two is high. However, the wait delay is negligible when the buffer size is increased beyond two. This is because increasing the buffer size reduces the head of line blocking. Thus more cells can move forward. Node delay and switched delay are comparable when the buffer size is greater than two. The delay offered is within a threshold range as noted for real time traffic. The delay is clock rate dependent and can be minimized by running the switching node at a higher clock speed. The worst delay noted for a switched cell for a node operating at a clock rate of 200 Mhz is 0.5 usec.
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Date Issued: 1992
PURL: http://purl.flvc.org/fcla/dt/12309
Subject Headings: Computer networks, Computer architecture, Packet switching (Data transmission)
Format: Document (PDF)

Title: Hierarchical design, simulation and synthesis of a RISC processor using computer-aided design tools.
Creator: Freytag, Glenn A., Florida Atlantic University, Marcovitz, Alan B.
Abstract/Description: The techniques employed in integrated circuit (IC) design have advanced significantly in the past decade. Design automation tools now offer hardware description languages (HDLs) for modeling and testing new designs. Some tools can even synthesize an IC from a model written in an HDL. Such design tools promise to facilitate greatly the development of new IC designs. They also make it possible for engineering students to learn advanced techniques of IC design and computer architecture in a...
Show moreThe techniques employed in integrated circuit (IC) design have advanced significantly in the past decade. Design automation tools now offer hardware description languages (HDLs) for modeling and testing new designs. Some tools can even synthesize an IC from a model written in an HDL. Such design tools promise to facilitate greatly the development of new IC designs. They also make it possible for engineering students to learn advanced techniques of IC design and computer architecture in a classroom setting. Two examples of such state-of-the-art design tools are Design Framework and Epoch. In this work, we present a hierarchical design for a reduced-instruction-set computer (RISC) processor, which we implemented using Design Framework and Epoch. The processor is based on the DLX architecture proposed by Hennessy and Patterson. We implemented our design according to a top-down methodology, which worked very well in these design tools.
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Date Issued: 1995
PURL: http://purl.flvc.org/fcla/dt/15220
Subject Headings: RISC microprocessors, Computer architecture, Computer-aided design
Format: Document (PDF)

Title: A heterogeneous multiprocessor architecture for workstations.
Creator: Bealkowski, Richard., Florida Atlantic University, Fernandez, Eduardo B., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Providing multiprocessor capability to the class of computers commonly referred to as personal workstations is the next evolutionary step in their development. Uniprocessor workstations limit the user in throughput, reliability, functionality, and architecture. Multiprocessor workstations have the potential of increasing system throughput. A multiprocessor system with expanded architecture derived from a set of heterogeneous processors gives the user a diverse application base within a single...
Show moreProviding multiprocessor capability to the class of computers commonly referred to as personal workstations is the next evolutionary step in their development. Uniprocessor workstations limit the user in throughput, reliability, functionality, and architecture. Multiprocessor workstations have the potential of increasing system throughput. A multiprocessor system with expanded architecture derived from a set of heterogeneous processors gives the user a diverse application base within a single system. The replication and diversity offered in systems of this design, when coupled with fault-tolerant design techniques, enhances system reliability. A heterogeneous multiprocessor architecture is presented which combines loosely- and tightly-coupled configurations (multicomputer and multiprocessor). This architecture provides for incremental growth of the system, either by static or dynamic reconfiguration. The software view of the system is that of an object-oriented environment. The object-oriented approach is used to unify the heterogeneous nature of the system. The process is the unit of concurrency in the system and cooperating concurrent processes are supported. A set of system primitives are provided to support the requirements of a heterogeneous multiprocessing environment. A virtual machine layer controls the distribution of processes and allocation of resources in the system. A virtual network is used to provide communication paths and resource sharing. The virtual network is designed to be bridged to an external physical network. The system requirements for a secure and reliable operating environment are incorporated into the design. This system utilizes "hardware porting" as a means to overcome the lag of software support for hardware advances. Rather than software port an entire application base to a new system architecture, hardware porting brings the required instruction set architecture to the applications. This heterogeneous multiprocessor architecture builds on a popular system architecture, the scIBM PS/2 with the Micro Channel system bus. Incorporating a second bus, the scSCSI bus, as a system extension is explored.
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Date Issued: 1989
PURL: http://purl.flvc.org/fcla/dt/12242
Subject Headings: Microcomputer workstations, Multiprocessors, Object-oriented programming (Computer science), Computer architecture
Format: Document (PDF)

Title: Framework for requirements-driven system design automation.
Creator: Fonoage, Mihai., Charles E. Schmidt College of Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: In this thesis, a framework for improving model-driven system design productivity with Requirements-Driven Design Automation (RDDA) is presented. The key to the proposed approach is to close the semantic gap between requirements, components and architecture by using compatible semantic models for describing product requirements and component capabilities, including constraints. An ontology-based representation language is designed that spans requirements for the application domain, the...
Show moreIn this thesis, a framework for improving model-driven system design productivity with Requirements-Driven Design Automation (RDDA) is presented. The key to the proposed approach is to close the semantic gap between requirements, components and architecture by using compatible semantic models for describing product requirements and component capabilities, including constraints. An ontology-based representation language is designed that spans requirements for the application domain, the software design domain and the component domain. Design automation is supported for architecture development by machine-based mapping of desired product/subsystem features and capabilities to library components and by synthesis and maintenance of Systems Modeling Language (SysML) design structure diagrams. The RDDA framework uses standards-based semantic web technologies and can be integrated with exiting modeling tools. Requirements specification is a major component of the system development cycle. Mistakes and omissions in requirements documents lead to ambiguous or wrong interpretation by engineers, causing errors that trickle down in design and implementation with consequences on the overall development cost. We describe a methodology for requirements specification that aims to alleviate the above issues and that produces models for functional requirements that can be automatically validated for completeness and consistency. The RDDA framework uses an ontology-based language for semantic description of functional product requirements, SysML structure diagrams, component constraints, and Quality of Service. The front-end method for requirements specification is the SysML editor in Rhapsody. A requirements model in Web Ontology Language (OWL) is converted from SysML to Extensible Markup Language Metadata Interchange (XMI) representation., The specification is validated for completeness and consistency with a ruled-based system implemented in Prolog. With our methodology, omission s and several types of consistency errors present in the requirements specification are detected early on, before the design stage. Component selection and design automation have the potential to play a major role in reducing the system development time and cost caused by the rapid change in technology advances and the large solution search space. In our work, we start from a structured representation of requirements and components using SysML, and based on specific set of rules written in Prolog, we partially automate the process of architecture design.
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Date Issued: 2010
PURL: http://purl.flvc.org/FAU/2975246
Subject Headings: Computer architecture, Computer software, Development, User-centered system design, Information technology, Management, Semantic Web
Format: Document (PDF)

Title: Fault-tolerant multicasting in hypercube multicomputers.
Creator: Yao, Kejun., Florida Atlantic University, Wu, Jie, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Interprocessor communication plays an important role in the performance of multicomputer systems, such as hypercube multicomputers. In this thesis, we consider the multicast problem for a hypercube system in the presence of faulty components. Two types of algorithms are proposed. Type 1 algorithms, which are developed based on local network information, can tolerate both node failures and link failures. Type 2 algorithms, which are developed based on limited global network information, ensure...
Show moreInterprocessor communication plays an important role in the performance of multicomputer systems, such as hypercube multicomputers. In this thesis, we consider the multicast problem for a hypercube system in the presence of faulty components. Two types of algorithms are proposed. Type 1 algorithms, which are developed based on local network information, can tolerate both node failures and link failures. Type 2 algorithms, which are developed based on limited global network information, ensure that each destination receives message through the shortest path. Simulation results show that type 2 algorithms achieve very good results on both time and traffic steps, two main criteria in measuring the performance of interprocessor communication.
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Date Issued: 1993
PURL: http://purl.flvc.org/fcla/dt/14896
Subject Headings: Hypercube networks (Computer networks), Computer architecture, Fault-tolerant computing
Format: Document (PDF)

Title: A fault-tolerant memory architecture for storing one hour of D-1 video in real time on long polyimide tapes.
Creator: Monteiro, Pedro Cox de Sousa., Florida Atlantic University, Glenn, William E., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Research is under way to fabricate large-area thin-film transistor arrays produced on a thin polyimide substrate. The polyimide substrate is available in long thirty centimeter wide rolls of tape, and lithography hardware is being developed to expose hundreds of meters of this tape with electrically addressable light modulators which can resolve 2 $\mu$m features. A fault-tolerant memory architecture is proposed that is capable of storing one hour of D-1 component digital video (almost 10^12...
Show moreResearch is under way to fabricate large-area thin-film transistor arrays produced on a thin polyimide substrate. The polyimide substrate is available in long thirty centimeter wide rolls of tape, and lithography hardware is being developed to expose hundreds of meters of this tape with electrically addressable light modulators which can resolve 2 $\mu$m features. A fault-tolerant memory architecture is proposed that is capable of storing one hour of D-1 component digital video (almost 10^12 bits) in real-time, on eight two-hundred meter long tapes. Appropriate error correcting codes and error concealment are proposed to compensate for drop-outs resulting from manufacturing defects so as to yield video images with error rates low enough to survive several generations of copies.
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Date Issued: 1992
PURL: http://purl.flvc.org/fcla/dt/14869
Subject Headings: Polyimides, Computer architecture, Memory hierarchy (Computer science), Fault-tolerant computing
Format: Document (PDF)

Title: An efficient and scalable core allocation strategy for multicore systems.
Creator: Rani, Manira S., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Multiple threads can run concurrently on multiple cores in a multicore system and improve performance/power ratio. However, effective core allocation in multicore and manycore systems is very challenging. In this thesis, we propose an effective and scalable core allocation strategy for multicore systems to achieve optimal core utilization by reducing both internal and external fragmentations. Our proposed strategy helps evenly spreading the servicing cores on the chip to facilitate better...
Show moreMultiple threads can run concurrently on multiple cores in a multicore system and improve performance/power ratio. However, effective core allocation in multicore and manycore systems is very challenging. In this thesis, we propose an effective and scalable core allocation strategy for multicore systems to achieve optimal core utilization by reducing both internal and external fragmentations. Our proposed strategy helps evenly spreading the servicing cores on the chip to facilitate better heat dissipation. We introduce a multi-stage power management scheme to reduce the total power consumption by managing the power states of the cores. We simulate three multicore systems, with 16, 32, and 64 cores, respectively, using synthetic workload. Experimental results show that our proposed strategy performs better than Square-shaped, Rectangle-shaped, L-Shaped, and Hybrid (contiguous and non-contiguous) schemes in multicore systems in terms of fragmentation and completion time. Among these strategies, our strategy provides a better heat dissipation mechanism.
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Date Issued: 2011
PURL: http://purl.flvc.org/FAU/3172698
Subject Headings: Modularity (Engineering), Multicasting (Computer networks), Convergence (Telecommunication), Computer architecture, Memory management (Computer science), Cache memory
Format: Document (PDF)

Title: Design and performance analysis of FDDI and DQDB network architectures.
Creator: Khera, Harbinder Singh., Florida Atlantic University, Ilyas, Mohammad, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: The primary emphasis of this thesis is to study the behavioral characteristics of Fiber Distributed Data Interface (FDDI) and Distributed Queue Dual Bus (DQDB) High Speed Local Area Networks (HSLANs). An FDDI architecture with passive interfaces is proposed to provide a reliable and efficient network topology. This network architecture outperforms the existing FDDI architecture with active interfaces in terms of small asynchronous packet delays and high asynchronous packet throughput. The...
Show moreThe primary emphasis of this thesis is to study the behavioral characteristics of Fiber Distributed Data Interface (FDDI) and Distributed Queue Dual Bus (DQDB) High Speed Local Area Networks (HSLANs). An FDDI architecture with passive interfaces is proposed to provide a reliable and efficient network topology. This network architecture outperforms the existing FDDI architecture with active interfaces in terms of small asynchronous packet delays and high asynchronous packet throughput. The design and implementation issues involved in the design of the hierarchical (multi-level) DQDB and FDDI networks are also presented. The hierarchical network architecture provides modularity and scalability with respect to speed and the number of users. Simulation models are developed for each of these network architectures to study their performance. Simulation results are presented in terms of medium access delay, throughput, and packet delays.
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Date Issued: 1993
PURL: http://purl.flvc.org/fcla/dt/14976
Subject Headings: Fiber Distributed Data Interface (Computer network standard), Computer architecture, Local area networks (Computer networks)
Format: Document (PDF)

Title: Cross-Layer Network Design using Controllers.
Creator: Slavik, Michael J., Mahgoub, Imad, Florida Atlantic University, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: A cross-layer design architecture featuring a new network stack component called a controller is presented. The controller takes system status information from the protocol components and uses it to tune the behavior of the network stack to a given performance objective. A controller design strategy using a machine learning algorithm and a simulator is proposed, implemented, and tested. Results show the architecture and design strategy are capable of producing a network stack that outperforms...
Show moreA cross-layer design architecture featuring a new network stack component called a controller is presented. The controller takes system status information from the protocol components and uses it to tune the behavior of the network stack to a given performance objective. A controller design strategy using a machine learning algorithm and a simulator is proposed, implemented, and tested. Results show the architecture and design strategy are capable of producing a network stack that outperforms the existing protocol stack for arbitrary performance objectives. The techniques presented give network designers the flexibility to easily tune the performance of their networks to suit their application. This cognitive networking architecture has great potential for high performance in future wireless networks.
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Date Issued: 2007
PURL: http://purl.flvc.org/fau/fd/FA00012555
Subject Headings: Computer architecture, Wireless communication systems--Design and construction, Evolutionary programming (Computer science), Mathematical optimization
Format: Document (PDF)

Fault-tolerant computing (4)	+ -
Hypercube networks (Computer networks) (3)	+ -
Multiprocessors (3)	+ -
Computer-aided design (2)	+ -
Object-oriented programming (Computer science) (2)	+ -

Packet switching (Data transmission) (2)	+ -
Parallel processing (Electronic computers) (2)	+ -
System design (2)	+ -
CONCORD (Computer architecture) (1)	+ -
Cache memory (1)	+ -
Cluster analysis (1)	+ -
Cluster analysis--Computer programs (1)	+ -
Computer algorithms (1)	+ -
Computer network architectures (1)	+ -
Computer network protocols (1)	+ -
Computer networks (1)	+ -
Computer networks -- Security measures (1)	+ -
Computer networks--Security measures (1)	+ -
Computer simulation (1)	+ -
Computer software (1)	+ -
Convergence (Telecommunication) (1)	+ -
Data processing (1)	+ -
Database management (1)	+ -
Design and construction (1)	+ -
Development (1)	+ -
Digital techniques (1)	+ -
Embedded computer systems (1)	+ -
Engineering design (1)	+ -
Evolutionary programming (Computer science) (1)	+ -

Florida Atlantic University (21)	+ -
Department of Computer and Electrical Engineering and Computer Science (20)	+ -
College of Engineering and Computer Science (19)	+ -
Mahgoub, Imad (5)	+ -
Shankar, Ravi (5)	+ -

Fernandez, Eduardo B. (3)	+ -
Wu, Jie (3)	+ -
Ilyas, Mohammad (2)	+ -
Asaduzzaman, Abu Sadath Mohammad (1)	+ -
Bealkowski, Richard. (1)	+ -
Calvert, Chad. (1)	+ -
Cang, Songluan. (1)	+ -
Charles E. Schmidt College of Science (1)	+ -
De Armas, Mario Ernesto. (1)	+ -
Fonoage, Mihai. (1)	+ -
Freytag, Glenn A. (1)	+ -
Glenn, William E. (1)	+ -
Gluch, David P. (1)	+ -
Hsu, Sam (1)	+ -
Huang, Chien-Jen (1)	+ -
Islam, Sifat (1)	+ -
Jain, Ankit. (1)	+ -
Jayadevappa, Suryaprasad. (1)	+ -
Karaali, Orhan. (1)	+ -
Khera, Harbinder Singh. (1)	+ -
Kumar, Ajoy (1)	+ -
Marcovitz, Alan B. (1)	+ -
Monteiro, Pedro Cox de Sousa. (1)	+ -
Mutha, Mahesh. (1)	+ -
Obeng, Morrison Stephen. (1)	+ -

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