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Title: TOWARDS A SECURITY REFERENCE ARCHITECTURE FOR NETWORK FUNCTION VIRTUALIZATION.
Creator: Alnaim, Abdulrahman K., Fernandez, Eduardo B., Florida Atlantic University, Department of Computer and Electrical Engineering and Computer Science, College of Engineering and Computer Science
Abstract/Description: Network Function Virtualization (NFV) is an emerging technology that transforms legacy hardware-based network infrastructure into software-based virtualized networks. Instead of using dedicated hardware and network equipment, NFV relies on cloud and virtualization technologies to deliver network services to its users. These virtualized network services are considered better solutions than hardware-based network functions because their resources can be dynamically increased upon the consumer’s...
Show moreNetwork Function Virtualization (NFV) is an emerging technology that transforms legacy hardware-based network infrastructure into software-based virtualized networks. Instead of using dedicated hardware and network equipment, NFV relies on cloud and virtualization technologies to deliver network services to its users. These virtualized network services are considered better solutions than hardware-based network functions because their resources can be dynamically increased upon the consumer’s request. While their usefulness can’t be denied, they also have some security implications. In complex systems like NFV, the threats can come from a variety of domains due to it containing both the hardware and the virtualize entities in its infrastructure. Also, since it relies on software, the network service in NFV can be manipulated by external entities like third-party providers or consumers. This leads the NFV to have a larger attack surface than the traditional network infrastructure. In addition to its own threats, NFV also inherits security threats from its underlying cloud infrastructure. Therefore, to design a secure NFV system and utilize its full potential, we must have a good understanding of its underlying architecture and its possible security threats. Up until now, only imprecise models of this architecture existed. We try to improve this situation by using architectural modeling to describe and analyze the threats to NFV. Architectural modeling using Patterns and Reference Architectures (RAs) applies abstraction, which helps to reduce the complexity of NFV systems by defining their components at their highest level. The literature lacks attempts to implement this approach to analyze NFV threats. We started by enumerating the possible threats that may jeopardize the NFV system. Then, we performed an analysis of the threats to identify the possible misuses that could be performed from them. These threats are realized in the form of misuse patterns that show how an attack is performed from the point of view of attackers. Some of the most important threats are privilege escalation, virtual machine escape, and distributed denial-of-service. We used a reference architecture of NFV to determine where to add security mechanisms in order to mitigate the identified threats. This produces our ultimate goal, which is building a security reference architecture for NFV.
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Date Issued: 2020
PURL: http://purl.flvc.org/fau/fd/FA00013435
Subject Headings: Computer network architectures--Safety measures, Virtual computer systems, Computer networks, Modeling, Computer
Format: Document (PDF)

Title: A REFERENCE ARCHITECTURE FOR NETWORK FUNCTION VIRTUALIZATION.
Creator: Alwakeel, Ahmed M., Fernandez, Eduardo B., Florida Atlantic University, Department of Computer and Electrical Engineering and Computer Science, College of Engineering and Computer Science
Abstract/Description: Cloud computing has provided many services to potential consumers, one of these services being the provision of network functions using virtualization. Network Function Virtualization is a new technology that aims to improve the way we consume network services. Legacy networking solutions are different because consumers must buy and install various hardware equipment. In NFV, networks are provided to users as a software as a service (SaaS). Implementing NFV comes with many benefits, including...
Show moreCloud computing has provided many services to potential consumers, one of these services being the provision of network functions using virtualization. Network Function Virtualization is a new technology that aims to improve the way we consume network services. Legacy networking solutions are different because consumers must buy and install various hardware equipment. In NFV, networks are provided to users as a software as a service (SaaS). Implementing NFV comes with many benefits, including faster module development for network functions, more rapid deployment, enhancement of the network on cloud infrastructures, and lowering the overall cost of having a network system. All these benefits can be achieved in NFV by turning physical network functions into Virtual Network Functions (VNFs). However, since this technology is still a new network paradigm, integrating this virtual environment into a legacy environment or even moving all together into NFV reflects on the complexity of adopting the NFV system. Also, a network service could be composed of several components that are provided by different service providers; this also increases the complexity and heterogeneity of the system. We apply abstract architectural modeling to describe and analyze the NFV architecture. We use architectural patterns to build a flexible NFV architecture to build a Reference Architecture (RA) for NFV that describe the system and how it works. RAs are proven to be a powerful solution to abstract complex systems that lacks semantics. Having an RA for NFV helps us understand the system and how it functions. It also helps us to expose the possible vulnerabilities that may lead to threats toward the system. In the future, this RA could be enhanced into SRA by adding misuse and security patterns for it to cover potential threats and vulnerabilities in the system. Our audiences are system designers, system architects, and security professionals who are interested in building a secure NFV system.
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Date Issued: 2020
PURL: http://purl.flvc.org/fau/fd/FA00013434
Subject Headings: Virtual computer systems, Cloud computing, Computer network architectures, Computer networks
Format: Document (PDF)

Title: Routing in mobile ad-hoc wireless networks.
Creator: Li, Hailan., Florida Atlantic University, Wu, Jie, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: This thesis describes routing in mobile ad hoc wireless networks. Ad hoc networks are lack of wired backbone to maintain routes as mobile hosts move and power is on or off. Therefore, the hosts in ad hoc networks must cooperate with each other to determine routes in a distributed manner. Routing based on a connected dominating set is a frequently used approach, where the searching space for a route is reduced to nodes in small connected dominating set subnetwork. We propose a simple and...
Show moreThis thesis describes routing in mobile ad hoc wireless networks. Ad hoc networks are lack of wired backbone to maintain routes as mobile hosts move and power is on or off. Therefore, the hosts in ad hoc networks must cooperate with each other to determine routes in a distributed manner. Routing based on a connected dominating set is a frequently used approach, where the searching space for a route is reduced to nodes in small connected dominating set subnetwork. We propose a simple and efficient distributed algorithm for calculating connected dominating set in a given un-directed ad hoc network, then evaluate the proposed algorithm through simulation. We also discuss connected dominating set update/recalculation algorithms when the topology of the ad hoc network changes. We also explore the possible extension of using hierarchical connected dominating set. The shortest path routing and the dynamic source routing, which are based on the connected dominating set subnetwork, are discussed.
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Date Issued: 1999
PURL: http://purl.flvc.org/fcla/dt/15695
Subject Headings: Mobile computing, Computer algorithms, Computer networks
Format: Document (PDF)

Title: Design and implementation of a wireless ad hoc network.
Creator: Neelakanta, Mahesh., Florida Atlantic University, Hsu, Sam, Ilyas, Mohammad, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: This thesis addresses issues faced in the practical implementation of a wireless ad hoc network (WAHN) protocol for data transmission. This study focuses on: (1) Evaluating existing hardware and software options available for the WAHN implementation. (2) Appraising the issues faced while implementing a practical wireless ad hoc protocol. (3) Applying a set of MAC protocol specifications developed for a wireless ad hoc data network to a practical test network. Specific to the above topics of...
Show moreThis thesis addresses issues faced in the practical implementation of a wireless ad hoc network (WAHN) protocol for data transmission. This study focuses on: (1) Evaluating existing hardware and software options available for the WAHN implementation. (2) Appraising the issues faced while implementing a practical wireless ad hoc protocol. (3) Applying a set of MAC protocol specifications developed for a wireless ad hoc data network to a practical test network. Specific to the above topics of interest, the following research tasks are performed: (1) An elaborate survey and relevant discussions on wireless MAC protocols. (2) A comprehensive study comparing various wireless transceivers is performed. Range, data rate, frequency, interfacing method and cost are the factors compared. (3) A simple, low-cost and low baud-rate transceiver is modified with appropriate interface circuits to support wireless communications. A more advanced transceiver is also considered and used for the software foundation of a practical implementation of the ad hoc and MAC protocols. The studies enable assessing the problems faced during the implementation and suggest solutions to resolve these problems. Further areas for study are also discussed.
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Date Issued: 1998
PURL: http://purl.flvc.org/fcla/dt/15615
Subject Headings: Wireless communication systems, Data transmission systems, Computer networks
Format: Document (PDF)

Title: Estimation of information-theoretics-based delay-bounds in ATM networks.
Creator: Wei, Liqun., Florida Atlantic University, Hsu, Sam, Neelakanta, Perambur S., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: This thesis addresses a method of deducing the statistical upper and lower bounds associated with the cell-transfer delay variations (CDVs) encountered by the cells transmitted in the asynchronous transfer mode (ATM) networks due to cell losses. This study focuses on: (1) Estimating CDV arising from multiplexing/switching for both constant bit rate and variable bit rate services via simulations. (2) Deducing an information-theoretics based new technique to get an insight of the combined BER...
Show moreThis thesis addresses a method of deducing the statistical upper and lower bounds associated with the cell-transfer delay variations (CDVs) encountered by the cells transmitted in the asynchronous transfer mode (ATM) networks due to cell losses. This study focuses on: (1) Estimating CDV arising from multiplexing/switching for both constant bit rate and variable bit rate services via simulations. (2) Deducing an information-theoretics based new technique to get an insight of the combined BER-induced and multiplexing/switching-induced CDVs in ATM networks. Algorithms on the CDV statistics are derived and the lower and upper bounds of the statistics are obtained via simulations in respect of CBR and VBR traffics. These bounds bounds are useful in the cell-admission control (CAC) strategies adapted in ATM transmissions. Inferential remarks indicating the effects of traffic parameters (such as bandwidth, burstiness etc.) on the values of the statistical bounds are presented, and scope for further work is indicated.
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Date Issued: 1997
PURL: http://purl.flvc.org/fcla/dt/15444
Subject Headings: Asynchronous transfer mode, Telecommunication, Computer networks, Broadband communication systems
Format: Document (PDF)

Title: A next generation computer network communications architecture.
Creator: Thor, Bernice Lynn., Florida Atlantic University, Ilyas, Mohammad, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: A Next Generation Computer Network Communications Architecture, CNCA, is developed in this thesis. Existing communication techniques and available networking technologies are explored. This provides the background information for the development of the architecture. Hardware, protocol, and interface requirements are addressed to provide a practical architecture for supporting high speed communications beyond current implementations. A reduction process is then performed to extract the optimal...
Show moreA Next Generation Computer Network Communications Architecture, CNCA, is developed in this thesis. Existing communication techniques and available networking technologies are explored. This provides the background information for the development of the architecture. Hardware, protocol, and interface requirements are addressed to provide a practical architecture for supporting high speed communications beyond current implementations. A reduction process is then performed to extract the optimal components for the CNCA platform. The resulting architecture describes a next generation communications device that is capable of very fast switching and fast processing of information. The architecture interfaces with existing products, and provides extensive flexibility. This protects existing equipment investments, and supports future enhancements.
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Date Issued: 1991
PURL: http://purl.flvc.org/fcla/dt/14726
Subject Headings: Computer network architectures, Computer networks
Format: Document (PDF)

Title: OPTIMAL SCHEDULING OF PROCESSES FOR A NETWORK OF TRANSPUTERS (MULTIPROCESSOR, OCCAM, CONCURRENT PROCESSING).
Creator: NGO, TON ANH., Florida Atlantic University, Fernandez, Eduardo B., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Concurrency at both the hardware and software level has recently been considered as the solution to the classic Von Neuman bottleneck in system design. Introduced by Inmos, the Occam language and the Transputer microprocessor provide simple and elegant building blocks for a concurrent system. This thesis proposes a set of algorithms to find an optimal deterministic schedule for an Occam program executed on a network of Transputers. Also discussed are features of the network relevant to the...
Show moreConcurrency at both the hardware and software level has recently been considered as the solution to the classic Von Neuman bottleneck in system design. Introduced by Inmos, the Occam language and the Transputer microprocessor provide simple and elegant building blocks for a concurrent system. This thesis proposes a set of algorithms to find an optimal deterministic schedule for an Occam program executed on a network of Transputers. Also discussed are features of the network relevant to the problem of scheduling, and a complete example is provided to illustrate the scheduler. The approaches described can be used as a basis for implementing a flexible general purpose multiprocessor system.
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Date Issued: 1986
PURL: http://purl.flvc.org/fcla/dt/14351
Subject Headings: Multiprocessors, Computer networks
Format: Document (PDF)

Title: PERFORMANCE EVALUATION OF THE EFFECTS OF MESSAGE SEGMENTATION IN TANDEM NODE COMPUTER NETWORKS.
Creator: LAMANNA, PETER JOHN., Florida Atlantic University, Ilyas, Mohammad, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Analytical and simulation performance evaluation results are presented on the effects of message segmentation and the validity of the Independence Assumption when applied to analytically modeling tandem node computer networks. Simulation results indicate that increasing message segmentation threshold will increase the network traffic intensity and consequently the total packet delay. Simulation and analytical results for total packet delay compared well only at low traffic intensities. At...
Show moreAnalytical and simulation performance evaluation results are presented on the effects of message segmentation and the validity of the Independence Assumption when applied to analytically modeling tandem node computer networks. Simulation results indicate that increasing message segmentation threshold will increase the network traffic intensity and consequently the total packet delay. Simulation and analytical results for total packet delay compared well only at low traffic intensities. At higher traffic intensities the discrepancy is due to the Independence Assumption since it does not account for the increasing dependency of interarrival times and service times as packets are made to wait at the nodes.
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Date Issued: 1986
PURL: http://purl.flvc.org/fcla/dt/14327
Subject Headings: Computer networks, Data transmission systems
Format: Document (PDF)

Title: GENERIC NETWORK EXECUTIVE.
Creator: SARMIENTO, JESUS LEOPOLDO., Florida Atlantic University, Fernandez, Eduardo B., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: A Generic Network Executive (GNE) package is presented in this thesis. It encompasses the strategy and methodology to follow when implementing data communication software. GNE was designed for portability and high utilization of available resources (efficiency). It does not impose implementation constraints because it does not include features specific to any system (hardware or operating system}. It uses a highly concurrent process model with a pipelined structure . It is not protocol...
Show moreA Generic Network Executive (GNE) package is presented in this thesis. It encompasses the strategy and methodology to follow when implementing data communication software. GNE was designed for portability and high utilization of available resources (efficiency). It does not impose implementation constraints because it does not include features specific to any system (hardware or operating system}. It uses a highly concurrent process model with a pipelined structure . It is not protocol dependent, rather it is meant to be used to implement low level services for higher level communic ation protocols. It is intended to provide interprocess communication in distributed systems by coupling application programs with a general purpose packet delivery system, i.e., a datagram service.
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Date Issued: 1986
PURL: http://purl.flvc.org/fcla/dt/14321
Subject Headings: Computer networks, Data transmission systems
Format: Document (PDF)

Title: Performance analysis of a new object-based I/O architecture for PCs and workstations.
Creator: Huynh, Khoa Dang., Florida Atlantic University, Khoshgoftaar, Taghi M., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: In this dissertation, an object-based I/O architecture for personal computers (PCs) and workstations is proposed. The proposed architecture allows the flexibility of having I/O processing performed as much as possible by intelligent I/O adapters, or by the host processor, or by any processor in the system, depending on application requirements and underlying hardware capabilities. It keeps many good features of current I/O architectures, while providing more flexibility to take advantage of...
Show moreIn this dissertation, an object-based I/O architecture for personal computers (PCs) and workstations is proposed. The proposed architecture allows the flexibility of having I/O processing performed as much as possible by intelligent I/O adapters, or by the host processor, or by any processor in the system, depending on application requirements and underlying hardware capabilities. It keeps many good features of current I/O architectures, while providing more flexibility to take advantage of new hardware technologies, promote architectural openness, provide better performance and higher reliability. The proposed architecture introduces a new definition of I/O subsystems and makes use of concurrent object-oriented technology. It combines the notions of object and thread into something called an active object. All concurrency abstractions required by the proposed architecture are provided through external libraries on top of existing sequential object-oriented languages, without any changes to the syntax and semantics of these languages. We also evaluate the performance of optimal implementations of the proposed I/O architecture against other I/O architectures in three popular, PC-based, distributed environments: network file server, video server, and video conferencing. Using the RESearch Queueing Modeling Environment (RESQME), we have developed detailed simulation models for various implementations of the proposed I/O architecture and two other existing I/O architectures: a conventional, interrupt-based I/O architecture and a peer-to-peer I/O architecture. Our simulation results indicate that, on several different hardware platforms, the proposed I/O architecture outperforms both existing architectures in all three distributed environments considered.
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Date Issued: 1994
PURL: http://purl.flvc.org/fcla/dt/12386
Subject Headings: Local area networks (Computer networks), Computer input-output equipment, Computer networks, Videoconferencing, Client/server computing, Object-oriented programming (Computer science)
Format: Document (PDF)

Title: Fault-tolerant distributed shared memories.
Creator: Brown, Larry., Florida Atlantic University, Wu, Jie, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Distributed shared memory (DSM) implements a shared-memory programming interface on message-passing hardware. The shared-memory programming paradigm offers several advantages over the message-passing paradigm. DSM is recognized as an important technology for massively parallel computing. However, as the number of processors in a system increases, the probability of a failure increases. To be widely useful, the DSM must be able to tolerate failures. This dissertation presents a method of...
Show moreDistributed shared memory (DSM) implements a shared-memory programming interface on message-passing hardware. The shared-memory programming paradigm offers several advantages over the message-passing paradigm. DSM is recognized as an important technology for massively parallel computing. However, as the number of processors in a system increases, the probability of a failure increases. To be widely useful, the DSM must be able to tolerate failures. This dissertation presents a method of implementing fault-tolerant DSM (FTDSM) that is based on the idea of a snooper. The snooper monitors DSM protocol messages and keeps a backup of the current state of the DSM. The snooper can respond on behalf of failed processors. The snooper-based FTDSM is an improvement over existing FTDSMs because it is based on the efficient dynamic distributed manager DSM algorithm, does not require the repair of a failed processor in access the DSM, and does not query all nodes to rebuild the state of the DSM. Three snooper-based FTDSM systems are developed. The single-snooper (SS) FTDSM has one snooper and is restricted to a broadcast network. Additional snoopers are added in the multiple-snooper (MS) FTDSM to improve performance. Two-phase commit (2PC) protocols are developed to coordinate the activities of the snoopers, and a special data structure is used to store causality information to reduce the amount of snooper activity. Snooping is integrated with each processor in the integrated snooper (IS) FTDSM. The IS FTDSM is scalable because it is not restricted to a broadcast network. The concept of dynamic snooping is introduced for the IS FTDSM and several snooper migration algorithms are studied. Several recovery algorithms are developed to allow failed processors to rejoin the system. The properties of data structures used to locate owners and snoopers are studied and used to prove that the system can tolerate any single fault. A flexible method of integrating application-level recovery with the FTDSM is presented, and a reliability analysis is conducted using a Markov-chain modeling tool to show that the snooper-based FTDSM is a cost effective way to improve the reliability of DSM.
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Date Issued: 1993
PURL: http://purl.flvc.org/fcla/dt/12349
Subject Headings: Fault-tolerant computing, Electronic data processing--Distributed processing, Parallel processing (Electronic computers), Computer networks
Format: Document (PDF)

Title: Learning in connectionist networks using the Alopex algorithm.
Creator: Venugopal, Kootala Pattath., Florida Atlantic University, Pandya, Abhijit S., Sudhakar, Raghavan, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: The Alopex algorithm is presented as a universal learning algorithm for connectionist models. It is shown that the Alopex procedure could be used efficiently as a supervised learning algorithm for such models. The algorithm is demonstrated successfully on a variety of network architectures. Such architectures include multilayer perceptrons, time-delay models, asymmetric, fully recurrent networks and memory neuron networks. The learning performance as well as the generation capability of the...
Show moreThe Alopex algorithm is presented as a universal learning algorithm for connectionist models. It is shown that the Alopex procedure could be used efficiently as a supervised learning algorithm for such models. The algorithm is demonstrated successfully on a variety of network architectures. Such architectures include multilayer perceptrons, time-delay models, asymmetric, fully recurrent networks and memory neuron networks. The learning performance as well as the generation capability of the Alopex algorithm are compared with those of the backpropagation procedure, concerning a number of benchmark problems, and it is shown that the Alopex has specific advantages over the backpropagation. Two new architectures (gain layer schemes) are proposed for the on-line, direct adaptive control of dynamical systems using neural networks. The proposed schemes are shown to provide better dynamic response and tracking characteristics, than the other existing direct control schemes. A velocity reference scheme is introduced to improve the dynamic response of on-line learning controllers. The proposed learning algorithm and architectures are studied on three practical problems; (i) Classification of handwritten digits using Fourier Descriptors; (ii) Recognition of underwater targets from sonar returns, considering temporal dependencies of consecutive returns and (iii) On-line learning control of autonomous underwater vehicles, starting with random initial conditions. Detailed studies are conducted on the learning control applications. Effect of the network learning rate on the tracking performance and dynamic response of the system are investigated. Also, the ability of the neural network controllers to adapt to slow and sudden varying parameter disturbances and measurement noise is studied in detail.
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Date Issued: 1993
PURL: http://purl.flvc.org/fcla/dt/12325
Subject Headings: Computer algorithms, Computer networks, Neural networks (Computer science), Machine learning
Format: Document (PDF)

Title: A high-speed switching node architecture for ATM networks.
Creator: Syed, Majid Ali, Florida Atlantic University, Ilyas, Mohammad, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: This research is aimed towards the concept of a new switching node architecture for cell-switched Asynchronous Transfer Mode (ATM) networks. The proposed architecture has several distinguishing features when compared with existing Banyan based switching node. It has a cylindrical structure as opposed to a flat structure as found in Banyans. The wrap around property results in better link utilization as compared with existing Banyans beside resulting in reduced average route length. Simplified...
Show moreThis research is aimed towards the concept of a new switching node architecture for cell-switched Asynchronous Transfer Mode (ATM) networks. The proposed architecture has several distinguishing features when compared with existing Banyan based switching node. It has a cylindrical structure as opposed to a flat structure as found in Banyans. The wrap around property results in better link utilization as compared with existing Banyans beside resulting in reduced average route length. Simplified digit controlled routing is maintained as found in Banyans. The cylindrical nature of the architecture, results in pipeline activity. Such architecture tends to sort the traffic to a higher address, eliminating the need of a preprocessing node as a front end processing node. Approximate Markov chain analyses for the performance of the switching node with single input buffers is presented. The analyses are used to compute the time delay distribution of a cell leaving the node. A simulation tool is used to validate the analytical model. The simulation model is free from the critical assumptions which are necessary to develop the analytical model. It is shown that the analytical results closely match with the simulation results. This confirms the authenticity of the simulation model. We then study the performance of the switching node for various input buffer sizes. Low throughput with single input buffered switching node is observed; however, as the buffer size is increased from two to three the increase in throughput is more than 100%. No appreciable increase in node delay is noted when the buffer size is increased from two to three. We conclude that the optimum buffer size for large throughput is three and the maximum throughput with offered load of 0.9 and buffer size three is 0.75. This is because of head of line blocking phenomenon. A technique to overcome such inherent problem is presented. Several delays which a cell faces are analyzed and summarized below. The wait delay with buffer sizes one and two is high. However, the wait delay is negligible when the buffer size is increased beyond two. This is because increasing the buffer size reduces the head of line blocking. Thus more cells can move forward. Node delay and switched delay are comparable when the buffer size is greater than two. The delay offered is within a threshold range as noted for real time traffic. The delay is clock rate dependent and can be minimized by running the switching node at a higher clock speed. The worst delay noted for a switched cell for a node operating at a clock rate of 200 Mhz is 0.5 usec.
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Date Issued: 1992
PURL: http://purl.flvc.org/fcla/dt/12309
Subject Headings: Computer networks, Computer architecture, Packet switching (Data transmission)
Format: Document (PDF)

Title: Specialized communications processor for layered protocols.
Creator: Mandalia, Baiju Dhirajlal., Florida Atlantic University, Ilyas, Mohammad, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: This dissertation describes an architecture for a special purpose communications protocol processor (CPP) that has been developed for open systems interconnection (OSI) type layered protocol processing. There exists a performance problem with the implementation and processing of communication protocols and the problem can have an impact on the throughput of future network interfaces. This problem revolves around two issues, (i) communication processing bottlenecks to fully utilize high speed...
Show moreThis dissertation describes an architecture for a special purpose communications protocol processor (CPP) that has been developed for open systems interconnection (OSI) type layered protocol processing. There exists a performance problem with the implementation and processing of communication protocols and the problem can have an impact on the throughput of future network interfaces. This problem revolves around two issues, (i) communication processing bottlenecks to fully utilize high speed transmission mediums; (ii) mechanism used in the implementation of communications functions. It is the objective of this work to address this problem and develop a first of its kind processor that is dedicated to protocol processing. At first trends in computer communications technology are discussed along with issues that influence throughput in front end controllers for network interfaces that support OSI. Network interface requirements and a survey of existing technology are presented and the state of the art of layered communication is evaluated and specific parameters that contribute to the performance of communications processors are identified. Based on this evaluation a new set of instructions is developed to support the necessary functions. Each component of the new architecture is explained with respect to the mechanism for implementation. The CPP contains special-purpose circuits dedicated to quick performance (e.g. single machine cycle execution) of functions needed to process header and frame information, functions which are repeatedly encountered in all protocol layers, and instructions designed to take advantage of these circuits. The header processing functions include priority branch determination functions, register bit reshaping (rearranging) functions, and instruction address processing functions. Frame processing functions include CRC (cyclic redundancy check) computations, bit insertion/deletion operations and special character detection operations. Justifications for new techniques are provided and their advantages over existing technology are discussed. A hardware register transfer level model is developed to simulate the new architecture for path length computations. A performance queueing model is also developed to analyze the processor characteristics with various load parameters. Finally, a brief discussion indicates how such a processor would apply to future network interfaces along with possible trends.
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Date Issued: 1989
PURL: http://purl.flvc.org/fcla/dt/11933
Subject Headings: Computer network protocols, Computer networks, Data transmission systems
Format: Document (PDF)

Title: A utility-based routing scheme in multi-hop wireless networks.
Creator: Lu, Mingming., College of Engineering and Computer Science, Florida Atlantic University, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Multi-hop wireless networks are infrastructure-less networks consisting of mobile or stationary wireless devices, which include multi-hop wireless mesh networks and multi-hop wireless sensor networks. These networks are characterized by limited bandwidth and energy resources, unreliable communication, and a lack of central control. These characteristics lead to the research challenges of multi-hop wireless networks. Building up routing schemes with good balance among the routing QoS (such as...
Show moreMulti-hop wireless networks are infrastructure-less networks consisting of mobile or stationary wireless devices, which include multi-hop wireless mesh networks and multi-hop wireless sensor networks. These networks are characterized by limited bandwidth and energy resources, unreliable communication, and a lack of central control. These characteristics lead to the research challenges of multi-hop wireless networks. Building up routing schemes with good balance among the routing QoS (such as reliability, cost, and delay) is a paramount concern to achieve high performance wireless networks. These QoS metrics are internally correlated. Most existing works did not fully utilize this correlation. We design a metric to balance the trade-off between reliability and cost, and build up a framework of utility-based routing model in multi-hop wireless networks. This dissertation focuses on the variations with applications of utility-based routing models, designing new concepts, and developing new algorithms for them. A review of existing routing algorithms and the basic utility-based routing model for multi-hop wireless networks has been provided at the beginning. An efficient algorithm, called MaxUtility, has been proposed for the basic utility-based routing model. MaxUtility is an optimal algorithm that can find the best routing path with the maximum expected utility., Various utility-based routing models are extended to further enhance the routing reliability while reducing the routing overhead. Besides computing the optimal path for a given benefit value and a given source-destination pair, the utility-based routing can be further extended to compute all optimal paths for all possible benefit values and/or all source-destination pairs. Our utility-based routing can also adapt to different applications and various environments. In the self-organized environment, where network users are selfish, we design a truthful routing, where selfish users have to tell the truth in order to maximize their utilities. We apply our utility-based routing scheme to the data-gathering wireless sensor networks, where a routing scheme is required to transmit data sensed by multiple sensor nodes to a common sink node.
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Date Issued: 2008
PURL: http://purl.flvc.org/FAU/77647
Subject Headings: Wireless communication systems, Security measures, Computer network protocols, Computer algorithms, Computer networks, Security measures
Format: Document (PDF)

Title: Analysis of quality of service (QoS) in WiMAX networks.
Creator: Talwalkar, Rohit., College of Engineering and Computer Science, Florida Atlantic University, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: In last few years there has been significant growth in the area of wireless communication. Quality of Service (QoS) has become an important consideration for supporting variety of applications that utilize the network resources. These applications include voice over IP, multimedia services, like, video streaming, video conferencing etc. IEEE 802.16/WiMAX is a new network which is designed with quality of service in mind. This thesis focuses on analysis of quality of service as implemented by...
Show moreIn last few years there has been significant growth in the area of wireless communication. Quality of Service (QoS) has become an important consideration for supporting variety of applications that utilize the network resources. These applications include voice over IP, multimedia services, like, video streaming, video conferencing etc. IEEE 802.16/WiMAX is a new network which is designed with quality of service in mind. This thesis focuses on analysis of quality of service as implemented by the WiMAX networks. First, it presents the details of the quality of service architecture in WiMAX network. In the analysis, a WiMAX module developed based on popular network simulator ns-2, is used. Various real life scenarios like voice call, video streaming are setup in the simulation environment. Parameters that indicate quality of service, such as, throughput, packet loss, average jitter and average delay, are analyzed for different types of service flows as defined in WiMAX. Results indicate that better quality of service is achieved by using service flows designed for specific applications.
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Date Issued: 2008
PURL: http://purl.flvc.org/fcla/flaent/EN00154040/68_2/98p0143h.pdf, http://purl.flvc.org/FAU/58012
Subject Headings: Wireless communication systems, Broadband communication systems, Wireless LANs, Design and construction, Computer networks, Management, Quality control
Format: Document (PDF)

Title: Probabilistic predictor-based routing in disruption-tolerant networks.
Creator: Yuan, Quan., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Disruption-Tolerant Networks (DTNs) are the networks comprised of a set of wireless nodes, and they experience unstable connectivity and frequent connection disruption because of the limitations of radio range, power, network density, device failure, and noise. DTNs are characterized by their lack of infrastructure, device limitation, and intermittent connectivity. Such characteristics make conventional wireless network routing protocols fail, as they are designed with the assumption the...
Show moreDisruption-Tolerant Networks (DTNs) are the networks comprised of a set of wireless nodes, and they experience unstable connectivity and frequent connection disruption because of the limitations of radio range, power, network density, device failure, and noise. DTNs are characterized by their lack of infrastructure, device limitation, and intermittent connectivity. Such characteristics make conventional wireless network routing protocols fail, as they are designed with the assumption the network stays connected. Thus, routing in DTNs becomes a challenging problem, due to the temporal scheduling element in a dynamic topology. One of the solutions is prediction-based, where nodes mobility is estimated with a history of observations. Then, the decision of forwarding messages during data delivery can be made with that predicted information. Current prediction-based routing protocols can be divided into two sub-categories in terms of that whether they are probability related: probabilistic and non-probabilistic. This dissertation focuses on the probabilistic prediction-based (PPB) routing schemes in DTNs. We find that most of these protocols are designed for a specified topology or scenario. So almost every protocol has some drawbacks when applied to a different scenario. Because every scenario has its own particular features, there could hardly exist a universal protocol which can suit all of the DTN scenarios. Based on the above motivation, we investigate and divide the current DTNs scenarios into three categories: Voronoi-based, landmark-based, and random moving DTNs. For each category, we design and implement a corresponding PPB routing protocol for either basic routing or a specified application with considering its unique features., Specifically, we introduce a Predict and Relay routing protocol for Voronoi-based DTNs, present a single-copy and a multi-copy PPB routing protocol for landmark-based DTNs, and propose DRIP, a dynamic Voronoi region-based publish/subscribe protocol, to adapt publish/subscribe systems to random moving DTNs. New concepts, approaches, and algorithms are introduced during our work.
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Date Issued: 2009
PURL: http://purl.flvc.org/FAU/359928
Subject Headings: Routers (Computer networks), Computer network protocols, Computer networks, Reliability, Computer algorithms, Wireless communication systems, Technological innovations
Format: Document (PDF)

Title: A reference architecture for cloud computing and its security applications.
Creator: Hashizume, Keiko., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Cloud Computing is security. In complex systems such as Cloud Computing, parts of a system are secured by using specific products, but there is rarely a global security analysis of the complete system. We have described how to add security to cloud systems and evaluate its security levels using a reference architecture. A reference architecture provides a framework for relating threats to the structure of the system and makes their numeration more systematic and complete. In order to secure a...
Show moreCloud Computing is security. In complex systems such as Cloud Computing, parts of a system are secured by using specific products, but there is rarely a global security analysis of the complete system. We have described how to add security to cloud systems and evaluate its security levels using a reference architecture. A reference architecture provides a framework for relating threats to the structure of the system and makes their numeration more systematic and complete. In order to secure a cloud framework, we have enumerated cloud threats by combining several methods because it is not possible to prove that we have covered all the threats. We have done a systematic enumeration of cloud threats by first identifying them in the literature and then by analyzing the activities from each of their use cases in order to find possible threats. These threats are realized in the form of misuse cases in order to understand how an attack happens from the point of view of an attacker. The reference architecture is used as a framework to determine where to add security in order to stop or mitigate these threats. This approach also implies to develop some security patterns which will be added to the reference architecture to design a secure framework for clouds. We finally evaluate its security level by using misuse patterns and considering the threat coverage of the models.
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Date Issued: 2013
PURL: http://purl.flvc.org/fcla/dt/3360787
Subject Headings: Computer networks, Design and construction, Cloud computing, Electronic data processing, Distributed processing
Format: Document (PDF)

Title: Web-based wireless sensor network monitoring using smartphones.
Creator: Marcus, Anthony M., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: This thesis consists of the development of a web based wireless sensor network (WSN) monitoring system using smartphones. Typical WSNs consist of networks of wireless sensor nodes dispersed over predetermined areas to acquire, process, and transmit data from these locations. Often it is the case that the WSNs are located in areas too hazardous or inaccessible to humans. We focused on the need for access to this sensed data remotely and present our reference architecture to solve this problem....
Show moreThis thesis consists of the development of a web based wireless sensor network (WSN) monitoring system using smartphones. Typical WSNs consist of networks of wireless sensor nodes dispersed over predetermined areas to acquire, process, and transmit data from these locations. Often it is the case that the WSNs are located in areas too hazardous or inaccessible to humans. We focused on the need for access to this sensed data remotely and present our reference architecture to solve this problem. We developed this architecture for web-based wireless sensor network monitoring and have implemented a prototype that uses Crossbow Mica sensors and Android smartphones for bridging the wireless sensor network with the web services for data storage and retrieval. Our application has the ability to retrieve sensed data directly from a wireless senor network composed of Mica sensors and from a smartphones onboard sensors. The data is displayed on the phone's screen, and then, via Internet connection, they are forwarded to a remote database for manipulation and storage. The attributes sensed and stored by our application are temperature, light, acceleration, GPS position, and geographical direction. Authorized personnel are able to retrieve and observe this data both textually and graphically from any browser with Internet connectivity or through a native Android application. Web-based wireless sensor network architectures using smartphones provides a scalable and expandable solution with applicability in many areas, such as healthcare, environmental monitoring, infrastructure health monitoring, border security, and others.
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Date Issued: 2011
PURL: http://purl.flvc.org/FAU/3171682
Subject Headings: Smartphones, Wireless communication systems, Security measures, Wireless communication systems, Technological innovations, Computer networks, Security measures, Ad hoc networks (Computer networks), Security measures
Format: Document (PDF)

Title: Adaptive power control in 802.11 networks.
Creator: Dural, Serkan., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: IEEE 802.11 networks successfully satisfy high data demands and are cheaper compared to cellular networks. Modern mobile computers and phones are equipped with 802.11 and are VoIP capable. Current network designs do not dynamically accommodate changes in the usage. We propose a dynamic power control algorithm that provides greater capacity within a limited geographic region. Most other power algorithms necessitate changes in 802.11 requiring hardware changes. Proposed algorithm only requires...
Show moreIEEE 802.11 networks successfully satisfy high data demands and are cheaper compared to cellular networks. Modern mobile computers and phones are equipped with 802.11 and are VoIP capable. Current network designs do not dynamically accommodate changes in the usage. We propose a dynamic power control algorithm that provides greater capacity within a limited geographic region. Most other power algorithms necessitate changes in 802.11 requiring hardware changes. Proposed algorithm only requires firmware updates to enable dynamic control of APs transmit power. We use earlier studies to determine the limit of the number of users to optimize power. By lowering transmit power of APs with large number of users, we can effectively decrease the cell size. The resulting gap is then covered by dynamically activating additional APs. This also provides greater flexibility and reduces the network planning costs.
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Date Issued: 2009
PURL: http://purl.flvc.org/FAU/221941
Subject Headings: IEEE 802.11 (Standard), Computer networks, Security measures, Computer network protocols, Mobile communication systems, Power supply
Format: Document (PDF)

Wireless communication systems (6)	+ -
Computer algorithms (5)	+ -
Computer network protocols (5)	+ -
Data transmission systems (4)	+ -
Security measures (4)	+ -

Computer network architectures (3)	+ -
Technological innovations (3)	+ -
Broadband communication systems (2)	+ -
Cloud computing (2)	+ -
Design and construction (2)	+ -
Management (2)	+ -
Reliability (2)	+ -
Telecommunication (2)	+ -
Virtual computer systems (2)	+ -
Access control (1)	+ -
Ad hoc networks (Computer networks) (1)	+ -
Asynchronous transfer mode (1)	+ -
Client/server computing (1)	+ -
Computer architecture (1)	+ -
Computer input-output equipment (1)	+ -
Computer network architectures--Safety measures (1)	+ -
Data encryption (Computer science) (1)	+ -
Digital signatures (1)	+ -
Distributed processing (1)	+ -
Electronic data processing (1)	+ -
Electronic data processing--Distributed processing (1)	+ -
Electronic digital computers (1)	+ -
Engineering economy (1)	+ -
Evaluation (1)	+ -

College of Engineering and Computer Science (24)	+ -
Florida Atlantic University (16)	+ -
Ilyas, Mohammad (5)	+ -
Fernandez, Eduardo B. (4)	+ -
Hashizume, Keiko. (2)	+ -

Hsu, Sam (2)	+ -
Wu, Jie (2)	+ -
Alnaim, Abdulrahman K. (1)	+ -
Alwakeel, Ahmed M. (1)	+ -
Brown, Larry. (1)	+ -
Dural, Serkan. (1)	+ -
Huynh, Khoa Dang. (1)	+ -
Khoshgoftaar, Taghi M. (1)	+ -
LAMANNA, PETER JOHN. (1)	+ -
Li, Hailan. (1)	+ -
Liu, Cong. (1)	+ -
Lu, Mingming. (1)	+ -
Mandalia, Baiju Dhirajlal. (1)	+ -
Marcus, Anthony M. (1)	+ -
NGO, TON ANH. (1)	+ -
Neelakanta, Mahesh. (1)	+ -
Neelakanta, Perambur S. (1)	+ -
Ortiz-Villajos, Jose M. (1)	+ -
Pandya, Abhijit S. (1)	+ -
SARMIENTO, JESUS LEOPOLDO. (1)	+ -
Sudhakar, Raghavan (1)	+ -
Syed, Majid Ali (1)	+ -
Talwalkar, Rohit. (1)	+ -
Thor, Bernice Lynn. (1)	+ -

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