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Title: Diagnosis of microprocessors using self-test and its application to multiprocessing.
Creator: Yazdani, Hamid R., Florida Atlantic University, Fernandez, Eduardo B., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: A great deal of research in the area of VLSI built-in testability is under way. This approach increases the reliability of the hardware system at the gate or circuit level. However, in many cases we cannot modify an existing hardware, and diagnostic software is a possible way to increase reliability. We use here a strategy to apply diagnostic tests that consist of starting of single units and instructions, to include progressively more complex instructions and units. After a complete...
Show moreA great deal of research in the area of VLSI built-in testability is under way. This approach increases the reliability of the hardware system at the gate or circuit level. However, in many cases we cannot modify an existing hardware, and diagnostic software is a possible way to increase reliability. We use here a strategy to apply diagnostic tests that consist of starting of single units and instructions, to include progressively more complex instructions and units. After a complete processor is shown to be correct, it can be used to test other processors in a multiprocessing system. We present here details of this approach, including self-test software and its application to the Intel 8086 microprocessor.
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Date Issued: 1987
PURL: http://purl.flvc.org/fcla/dt/14426
Subject Headings: Microprocessors--Testing
Format: Document (PDF)

Title: PERFORMANCE EVALUATION OF A RIDGE 32 COMPUTER SYSTEM (RISC (REDUCED INSTRUCTION SET COMPUTER)).
Creator: YOON, SEOK TAE., Florida Atlantic University, Fernandez, Eduardo B., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: As a new trend in designing a computer architecture, Reduced Instruction set Computers(RISC) have been proposed recently. This thesis reviews the new design approach behind the RISC and discuss the controversy between the proponents of the RISC approach and those of the traditional Complex Instruction set COmputer(CISC) approach. Ridge 32 is selected as a case study of the RISCs. Architectural parameters to evaluate the computer performance are considered to analyze the performance of the...
Show moreAs a new trend in designing a computer architecture, Reduced Instruction set Computers(RISC) have been proposed recently. This thesis reviews the new design approach behind the RISC and discuss the controversy between the proponents of the RISC approach and those of the traditional Complex Instruction set COmputer(CISC) approach. Ridge 32 is selected as a case study of the RISCs. Architectural parameters to evaluate the computer performance are considered to analyze the performance of the Ridge 32. A simulator for the Ridge 32 was implemented in PASCAL as a way of measuring those parameters. Measurement results on the several selected benchmark programs are given and analyzed to evaluate the characteristics of the Ridge 32.
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Date Issued: 1986
PURL: http://purl.flvc.org/fcla/dt/14348
Subject Headings: Computer architecture, Microprocessors
Format: Document (PDF)

Title: MICROPROCESSOR SONAR SYSTEM.
Creator: SHABIB, HASSAN MARWAN, Florida Atlantic University
Abstract/Description: This thesis presents the development of a microprocessor based navigational system. The integrated system is capable of determining depth to the bottom, distance to the surface, and velocity of a deep towed submersible. The system also alerts the user to any reduction to forward safe distance limit. A discussion of the hardware used to gather the data is presented. Software development is discussed in great detail. The system utilizes the Sixty Five Hundred microprocessor family. Advantages...
Show moreThis thesis presents the development of a microprocessor based navigational system. The integrated system is capable of determining depth to the bottom, distance to the surface, and velocity of a deep towed submersible. The system also alerts the user to any reduction to forward safe distance limit. A discussion of the hardware used to gather the data is presented. Software development is discussed in great detail. The system utilizes the Sixty Five Hundred microprocessor family. Advantages include cost effectiveness and application versatility.
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Date Issued: 1980
PURL: http://purl.flvc.org/fcla/dt/14008
Subject Headings: Microprocessors--Programming, Sonar
Format: Document (PDF)

Title: Microprocessor design for non-discretionary multilevel security.
Creator: Clifton, Daniel B., Florida Atlantic University, Fernandez, Eduardo B.
Abstract/Description: Microprocessor design for data security is examined with regard to both methodology and implementation. The examination begins with seven commercial 32-bit microprocessors which are evaluated against a set of previously published requirements for secure hardware. Then, the methodology and implementation of data secure microprocessor design is presented using an original design. The presentation includes a description of the security policy implemented, a model of secure operation, and a...
Show moreMicroprocessor design for data security is examined with regard to both methodology and implementation. The examination begins with seven commercial 32-bit microprocessors which are evaluated against a set of previously published requirements for secure hardware. Then, the methodology and implementation of data secure microprocessor design is presented using an original design. The presentation includes a description of the security policy implemented, a model of secure operation, and a detailed description of the design. The security-related overhead of the new design is compared to that of two commercial microprocessors. The design is then validated with a formal proof. Finally, the design is shown to protect against several generic attacks.
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Date Issued: 1988
PURL: http://purl.flvc.org/fcla/dt/14443
Subject Headings: Microprocessors, Data protection
Format: Document (PDF)

Title: PALSAM INPUT DATA FILE GENERATOR.
Creator: ROBINSON, WILLIAM ROBERT, JR., Florida Atlantic University, Marcovitz, Alan B., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: The capabilities and limitations of Programmable Array Logic devices (PALs) are presented and compared to other logic devices. PALs are field programmable devices and a program called PALSAM exists to assist the designer in programming PALs. The attributes and limitations of PALSAM are discussed. The PALSAM Input Data File Generator program was written to eliminate many of the limitations of PALSAM. The need for an algorithmic method of reducing a general logic expression to a minimal sum-of...
Show moreThe capabilities and limitations of Programmable Array Logic devices (PALs) are presented and compared to other logic devices. PALs are field programmable devices and a program called PALSAM exists to assist the designer in programming PALs. The attributes and limitations of PALSAM are discussed. The PALSAM Input Data File Generator program was written to eliminate many of the limitations of PALSAM. The need for an algorithmic method of reducing a general logic expression to a minimal sum-of-products form is demonstrated. Several algorithms are discussed. The Zissos, Duncan and Jones Algorithm, which claims to produce a minimal sum-of-products expression but is presented without proof by its authors, is disproved by example. A modification of this algorithm is presented without proof. When tested in the 276 possible cases involving up to three variables, this new algorithm always produced a minimal sum-of-products expression, while the original algorithm failed in six of these cases. Finally, the PALSAM Input Data File Generator program which uses the modified algorithm is presented and documented.
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Date Issued: 1984
PURL: http://purl.flvc.org/fcla/dt/14199
Subject Headings: Programmable array logic, Microprocessors--Programming, Algorithms
Format: Document (PDF)

Title: THE IMPLEMENTATION OF SOFTWARE FAULT TOLERANCE IN THE INTEL 80286 PROCESSOR.
Creator: OZAKI, BRENDA., Florida Atlantic University, Fernandez, Eduardo B., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: This thesis analyzes how the architecture of the Intel 80286 microprocessor may be used to implement fault tolerant software structures. The Multi-Micro Programming Line, MML, and the Intel 80286 kernel, K286, are used as tools to illustrate the implementation of software fault tolerance in an 80286 environment. The recovery metaprogram approach is supported by software layers which use the privilege levels in the 80286. Implementation of recovery blocks, N-version programming, exceptions,...
Show moreThis thesis analyzes how the architecture of the Intel 80286 microprocessor may be used to implement fault tolerant software structures. The Multi-Micro Programming Line, MML, and the Intel 80286 kernel, K286, are used as tools to illustrate the implementation of software fault tolerance in an 80286 environment. The recovery metaprogram approach is supported by software layers which use the privilege levels in the 80286. Implementation of recovery blocks, N-version programming, exceptions, and conversations using a recovery metaprogram are covered. While the details are specific to the 80286 architecture, the general results apply to any architecture with three or more rings of privilege and a segmented virtual memory using descriptors.
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Date Issued: 1987
PURL: http://purl.flvc.org/fcla/dt/14399
Subject Headings: Fault-tolerant computing, Intel 80286 (Microprocessor)
Format: Document (PDF)

Title: APPLICATION OF A MICROPROCESSOR TO ACOUSTIC DATA SAMPLING AND MANAGEMENT TASKS (AS APPLIED TO MANGANESE NODULE MINING).
Creator: MURPHY, DAVID PAUL, JR., Florida Atlantic University, Davidson, J. Blaine, College of Engineering and Computer Science, Department of Ocean and Mechanical Engineering
Abstract/Description: Methods of collecting information about the deep ocean sediments are considered. A compact, flexible data collection and management system based on microprocessor technology is developed. The hardware of the system is detailed and a typical software operating system is presented which controls sensor operations, stores temporary data and communicates with a shipboard computer system.
Date Issued: 1979
PURL: http://purl.flvc.org/fcla/dt/13987
Subject Headings: Microprocessors, Marine sediments--Sampling, Manganese nodules
Format: Document (PDF)

Title: The microprocessor design team assignment problem with a new multistage stochastic/Brownian motion model.
Creator: O'Grady, Thomas James., Florida Atlantic University, Han, Chingping (Jim), College of Engineering and Computer Science, Department of Ocean and Mechanical Engineering
Abstract/Description: The Microprocessor Design Team Assignment Problem models the microprocessor design efforts of Intel Corporation over a 29-year period from 1972 until 2001. The basic model is a Erlang queuing system based probability model of the individual programming-design team daily operations. After extensive research the Erlang Loss/Delay Blocked Multiserver Model is utilized throughout the dissertation The Erlang loss-delay model takes into account the Key Man Constraint for team leaders and...
Show moreThe Microprocessor Design Team Assignment Problem models the microprocessor design efforts of Intel Corporation over a 29-year period from 1972 until 2001. The basic model is a Erlang queuing system based probability model of the individual programming-design team daily operations. After extensive research the Erlang Loss/Delay Blocked Multiserver Model is utilized throughout the dissertation The Erlang loss-delay model takes into account the Key Man Constraint for team leaders and programming team personnel. The Microprocessor Design Team Assignment Problem Case Study and massive research effort, into Intel Corporations design efforts, is complicated by modeling a major programming-design team operation without any current data or assistance from Intel Corporation. However much of the lack of assistance and data was obtained by utilizing a critical managerial design team decomposition which answered most major questions about Intels lack of adequate personnel and overutilization of team leaders and asst. team leaders throughout the 48 months of most major design projects. The study-dissertation concludes that Intels and Hewlett Packards current positions in the computer industry are relatively secure because of extremely high entry level costs exceeding $850,000,000.00 million dollars. Many individual issues about programming-design team operations are analyzed in a great amount of detail. This is the first time that much of this design-programming team material and information is being made public for future research and continuing improvement upon large scale project managerial methods and techniques. The basic design-programming team effort is also modeled with Erlang probability models and stochastic Riccati differential equations. This modeling effort is discussed in great detail in chapter 5 and Appendix Alpha. It is believed that this fundamental research leads the way for more advanced efforts in manufacturing systems and possibly mechatronics for further models utilizing strong Markov properties. This research effort substantially advances the basic research and knowledge of Partially Observable Markov Decision Processes and Strong Brownian Motion with the basic unit being strong Markov properties.
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Date Issued: 2001
PURL: http://purl.flvc.org/fcla/dt/11962
Subject Headings: Brownian motion processes, Stochastic analysis, Microprocessors
Format: Document (PDF)

Title: Efficient Implementations of Post-quantum Isogeny-based Cryptography.
Creator: Jalali, Amir, Azarderakhsh, Reza, Florida Atlantic University, College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: Quantum computers are envisioned to be able to solve mathematical problems which are currently unsolvable for conventional computers, because of their exceptional computational power from quantum mechanics. Therefore, if quantum computers are ever built in large scale, they will certainly be able to solve many classical exponential complexity problems such as the hard problems which the current public key cryptography is constructed upon. To counteract this problem, the design of post-quantum...
Show moreQuantum computers are envisioned to be able to solve mathematical problems which are currently unsolvable for conventional computers, because of their exceptional computational power from quantum mechanics. Therefore, if quantum computers are ever built in large scale, they will certainly be able to solve many classical exponential complexity problems such as the hard problems which the current public key cryptography is constructed upon. To counteract this problem, the design of post-quantum cryptography protocols is necessary to preserve the security in the presence of quantum adversaries. Regardless of whether we can estimate the exact time for the advent of the quantum computing era, security protocols are required to be resistant against potentially-malicious power of quantum computing. In this thesis, the main focus is on the sperformance improvement of one of the potential PQC candidates, isogeny-based cryptography. Several optimized implementations of cryptography applications based on this primitive are presented. From a general viewpoint, the proposed methods, implementation techniques and libraries have a practical impact on the performance evaluation of post-quantum cryptography schemes in a wide range of applications. In particular, the provided benchmarks and optimizations on ARM-powered processors provide a reference for comparison and evaluation of isogeny-based cryptography with other post-quantum candidates during the first round of NIST's PQC standardization process.
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Date Issued: 2018
PURL: http://purl.flvc.org/fau/fd/FA00013125
Subject Headings: Cryptography, Quantum computing, ARM microprocessors, Post-quantum cryptography
Format: Document (PDF)

Title: Hierarchical design, simulation and synthesis of a RISC processor using computer-aided design tools.
Creator: Freytag, Glenn A., Florida Atlantic University, Marcovitz, Alan B.
Abstract/Description: The techniques employed in integrated circuit (IC) design have advanced significantly in the past decade. Design automation tools now offer hardware description languages (HDLs) for modeling and testing new designs. Some tools can even synthesize an IC from a model written in an HDL. Such design tools promise to facilitate greatly the development of new IC designs. They also make it possible for engineering students to learn advanced techniques of IC design and computer architecture in a...
Show moreThe techniques employed in integrated circuit (IC) design have advanced significantly in the past decade. Design automation tools now offer hardware description languages (HDLs) for modeling and testing new designs. Some tools can even synthesize an IC from a model written in an HDL. Such design tools promise to facilitate greatly the development of new IC designs. They also make it possible for engineering students to learn advanced techniques of IC design and computer architecture in a classroom setting. Two examples of such state-of-the-art design tools are Design Framework and Epoch. In this work, we present a hierarchical design for a reduced-instruction-set computer (RISC) processor, which we implemented using Design Framework and Epoch. The processor is based on the DLX architecture proposed by Hennessy and Patterson. We implemented our design according to a top-down methodology, which worked very well in these design tools.
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Date Issued: 1995
PURL: http://purl.flvc.org/fcla/dt/15220
Subject Headings: RISC microprocessors, Computer architecture, Computer-aided design
Format: Document (PDF)

Title: Software-implemented fault tolerance in a hypercube multiprocessor.
Creator: Sahai, Shankar., Florida Atlantic University, Fernandez, Eduardo B., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description: This thesis analyzes how software fault tolerance can be implemented in a hypercube multiprocessor. For concreteness we consider a multiprocessor using Intel 80286/386/486 processors. The Recovery Metaprogram approach (an architecture that isolates all fault tolerance functions in a special layer) has been used to implement application transparent and application specific fault tolerance technigues such as recovery blocks, N-version programming, exceptions and others. A fault tolerant routing...
Show moreThis thesis analyzes how software fault tolerance can be implemented in a hypercube multiprocessor. For concreteness we consider a multiprocessor using Intel 80286/386/486 processors. The Recovery Metaprogram approach (an architecture that isolates all fault tolerance functions in a special layer) has been used to implement application transparent and application specific fault tolerance technigues such as recovery blocks, N-version programming, exceptions and others. A fault tolerant routing algorithm is also described. While the details are specific to the 80286/386/486 processor these results apply also to any other processor with similar features.
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Date Issued: 1990
PURL: http://purl.flvc.org/fcla/dt/14633
Subject Headings: Hypercube networks (Computer networks), Intel 80x86 (Microprocessor)
Format: Document (PDF)

Title: CLASSICAL AND POST-QUANTUM CRYPTOGRAPHY ON MODERN ARM-BASED PROCESSORS.
Creator: Anastasova, Mila, Azarderakhsh, Reza, Florida Atlantic University, Department of Computer and Electrical Engineering and Computer Science, College of Engineering and Computer Science
Abstract/Description: Cryptographic algorithms are being developed and incorporated into network security protocols to provide secure communication over vulnerable mediums like the Internet. These protocols utilize secret and public key mechanisms to carry out data integrity, confidentiality, authentication, and non-repudiation. The urge to deploy cryptosystems on low-end devices, based on the constantly growing Internet of Things (IoT) world, requires optimal design and implementation of cryptographic algorithms...
Show moreCryptographic algorithms are being developed and incorporated into network security protocols to provide secure communication over vulnerable mediums like the Internet. These protocols utilize secret and public key mechanisms to carry out data integrity, confidentiality, authentication, and non-repudiation. The urge to deploy cryptosystems on low-end devices, based on the constantly growing Internet of Things (IoT) world, requires optimal design and implementation of cryptographic algorithms and protocols to achieve small communicational and computational cost, while preserving the privacy of the transmitted data. Scenarios of low bandwidth, constrained memory, and limited processing power are common when targeting embedded devices; however, security requirements are still present due to the sensitive information that may be communicated. In this thesis, we address the need for optimal cryptographic primitives implementation design in terms of computing capabilities, energy and power consumption, and memory usage to accommodate the deployment of cryptographical systems on resource-constrained devices.
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Date Issued: 2024
PURL: http://purl.flvc.org/fau/fd/FA00014431
Subject Headings: Cryptography, ARM microprocessors, Public key cryptography, Curves, Elliptic
Format: Document (PDF)

Title: Processor architectures for multimedia: A survey.
Creator: Furht, Borko
Date Issued: 1997-11-17 - 1997-11-20
PURL: http://purl.flvc.org/fcla/dt/345865
Subject Headings: Microprocessors --Design and construction., Streaming technology (Telecommunications), Broadband communication systems., Internetworking (Telecommunication), Multimedia systems.
Format: Document (PDF)

Title: Optimizing C for the M68HC11 processor.
Creator: Holzschuh, Susan M., Florida Atlantic University, Levow, Roy B.
Abstract/Description: The outputs of two available cross compilers for the M68HC11 processor are examined to develop an understanding of the conditions affecting the object code size efficiency of an optimizing C compiler for the M68HC11 processor. The types of optimizations that reduce the size of the code and are not currently implemented by these compilers are described and quantified. In addition, since the object code sizes of the C programs compiled by these compilers are considerably larger than the object...
Show moreThe outputs of two available cross compilers for the M68HC11 processor are examined to develop an understanding of the conditions affecting the object code size efficiency of an optimizing C compiler for the M68HC11 processor. The types of optimizations that reduce the size of the code and are not currently implemented by these compilers are described and quantified. In addition, since the object code sizes of the C programs compiled by these compilers are considerably larger than the object code sizes of comparable assembly language programs, these differences are also examined. The reasons for these differences are also described and quantified. Implementation recommendations are then presented.
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Date Issued: 1991
PURL: http://purl.flvc.org/fcla/dt/14745
Subject Headings: C (Computer program language), Compilers (Computer programs), Motorola 68000 series microprocessors
Format: Document (PDF)

FAU Theses and Dissertations (13)	+ -
FAU College Collections (1)	+ -

Microprocessors (4)	+ -
ARM microprocessors (2)	+ -
Computer architecture (2)	+ -
Cryptography (2)	+ -
Microprocessors--Programming (2)	+ -

Algorithms (1)	+ -
Broadband communication systems. (1)	+ -
Brownian motion processes (1)	+ -
C (Computer program language) (1)	+ -
Compilers (Computer programs) (1)	+ -
Computer-aided design (1)	+ -
Curves, Elliptic (1)	+ -
Data protection (1)	+ -
Fault-tolerant computing (1)	+ -
Hypercube networks (Computer networks) (1)	+ -
Intel 80286 (Microprocessor) (1)	+ -
Intel 80x86 (Microprocessor) (1)	+ -
Internetworking (Telecommunication) (1)	+ -
Manganese nodules (1)	+ -
Marine sediments--Sampling (1)	+ -
Microprocessors --Design and construction. (1)	+ -
Microprocessors--Testing (1)	+ -
Motorola 68000 series microprocessors (1)	+ -
Multimedia systems. (1)	+ -
Post-quantum cryptography (1)	+ -
Programmable array logic (1)	+ -
Public key cryptography (1)	+ -
Quantum computing (1)	+ -
RISC microprocessors (1)	+ -
Sonar (1)	+ -

Electronic Thesis or Dissertation (13)	+ -
article (1)	+ -

Florida Atlantic University (13)	+ -
College of Engineering and Computer Science (9)	+ -
Department of Computer and Electrical Engineering and Computer Science (7)	+ -
Fernandez, Eduardo B. (5)	+ -
Azarderakhsh, Reza (2)	+ -

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