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16 BIT TTL MINICOMPUTER FOR TELEPROCESSING
Title
A 16 BIT TTL MINICOMPUTER FOR TELEPROCESSING.
Creator
APPEL, WILLIAM DALE., Florida Atlantic University, Marcovitz, Alan B.
Abstract/Description
A 16 bit non-bussed minicomputer design exhibits significant performance advantages over the popular 8080 microcomputer. The design and operation of this device is discussed. Microcoding is employed only where it is a direct replacement for a needed combinatorial function and microcode formats are kept as simple as possible. Since it is anticipated that non-direct addressing will be used extensively in the eventual application of teleprocessing, special hardware is committed to this task. The...
Show moreA 16 bit non-bussed minicomputer design exhibits significant performance advantages over the popular 8080 microcomputer. The design and operation of this device is discussed. Microcoding is employed only where it is a direct replacement for a needed combinatorial function and microcode formats are kept as simple as possible. Since it is anticipated that non-direct addressing will be used extensively in the eventual application of teleprocessing, special hardware is committed to this task. The result is a significant speed advantage over typical address calculating schemes. Additional circuitry is provided to allow rapid subroutine entry, exit, and parameter fetching.
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Date Issued
1978
PURL
http://purl.flvc.org/fcla/dt/13926
Subject Headings
Minicomputers--Design and construction
Format
Document (PDF)
Hierarchical design, simulation and synthesis of a RISC processor using computer-aided design tools
Title
Hierarchical design, simulation and synthesis of a RISC processor using computer-aided design tools.
Creator
Freytag, Glenn A., Florida Atlantic University, Marcovitz, Alan B.
Abstract/Description
The techniques employed in integrated circuit (IC) design have advanced significantly in the past decade. Design automation tools now offer hardware description languages (HDLs) for modeling and testing new designs. Some tools can even synthesize an IC from a model written in an HDL. Such design tools promise to facilitate greatly the development of new IC designs. They also make it possible for engineering students to learn advanced techniques of IC design and computer architecture in a...
Show moreThe techniques employed in integrated circuit (IC) design have advanced significantly in the past decade. Design automation tools now offer hardware description languages (HDLs) for modeling and testing new designs. Some tools can even synthesize an IC from a model written in an HDL. Such design tools promise to facilitate greatly the development of new IC designs. They also make it possible for engineering students to learn advanced techniques of IC design and computer architecture in a classroom setting. Two examples of such state-of-the-art design tools are Design Framework and Epoch. In this work, we present a hierarchical design for a reduced-instruction-set computer (RISC) processor, which we implemented using Design Framework and Epoch. The processor is based on the DLX architecture proposed by Hennessy and Patterson. We implemented our design according to a top-down methodology, which worked very well in these design tools.
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Date Issued
1995
PURL
http://purl.flvc.org/fcla/dt/15220
Subject Headings
RISC microprocessors, Computer architecture, Computer-aided design
Format
Document (PDF)
APPLICATION OF DATA COMPRESSION TECHNIQUES ON COMPUTER-BASED TEXT AND PROGRAM SOURCE LIBRARIES
Title
APPLICATION OF DATA COMPRESSION TECHNIQUES ON COMPUTER-BASED TEXT AND PROGRAM SOURCE LIBRARIES.
Creator
FLOYD, RAYMOND EDWARD., Florida Atlantic University, Marcovitz, Alan B.
Abstract/Description
Data compression in computer based data files has just begun to be used, with the major emphasis placed on character string suppression. Within this paper, character string suppression, Huffman encoding, noun-vector, and dictionary-vector compression methods are reviewed and compared as well as several combinations of these methods. The methods investigated were compared against three typical data library types: 1) program source data files, 2) test case data files, and 3) text data files....
Show moreData compression in computer based data files has just begun to be used, with the major emphasis placed on character string suppression. Within this paper, character string suppression, Huffman encoding, noun-vector, and dictionary-vector compression methods are reviewed and compared as well as several combinations of these methods. The methods investigated were compared against three typical data library types: 1) program source data files, 2) test case data files, and 3) text data files. Compression percentage, speed of compression and decompression, storage requirements, error recovery, and data security comparison of the various methods are also presented.
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Date Issued
1977
PURL
http://purl.flvc.org/fcla/dt/13852
Subject Headings
Data compression (Computer science), Data libraries--Automation
Format
Document (PDF)
USING A SYNCHRONOUS SYSTEM ARCHITECTURE TO BUILD A LOW COST GRAPHICS TERMINAL
Title
USING A SYNCHRONOUS SYSTEM ARCHITECTURE TO BUILD A LOW COST GRAPHICS TERMINAL.
Creator
DEAN, MARK EDWARD., Florida Atlantic University, Marcovitz, Alan B.
Abstract/Description
Computer generated graphics has become an integral part of most computer systems. Communicating information in an interesting and understandable manner has become a necessity in the computer industry due to the increase in users who are interested in animation, simulation, graphical design, games and graphic representations of complex mathematical information. The Synchronous System Architecture described in this paper will illustrate a simple, low cost and efficient means of creating and...
Show moreComputer generated graphics has become an integral part of most computer systems. Communicating information in an interesting and understandable manner has become a necessity in the computer industry due to the increase in users who are interested in animation, simulation, graphical design, games and graphic representations of complex mathematical information. The Synchronous System Architecture described in this paper will illustrate a simple, low cost and efficient means of creating and displaying images on a cathode ray tube (CRT). A step-by-step design procedure is presented which utilizes the Synchronous System Architecture (SSA) in a standalone system/terminal environment. Finally, the software alogrithms used in the system will be outlined and discussed.
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Date Issued
1982
PURL
http://purl.flvc.org/fcla/dt/14100
Subject Headings
Computer graphics
Format
Document (PDF)
ANALYSIS AND COMPARISON OF THE RELEASE WHEN DONE AND RELEASE ON REQUEST BUS ARBITRATION METHODS (MAKOV CHAIN, MULTIPROCESSOR, BUS MASTER)
Title
ANALYSIS AND COMPARISON OF THE RELEASE WHEN DONE AND RELEASE ON REQUEST BUS ARBITRATION METHODS (MAKOV CHAIN, MULTIPROCESSOR, BUS MASTER).
Creator
SINIBALDI, JOHN CLAUDE., Florida Atlantic University, Marcovitz, Alan B., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description
A comparative analysis of two methods of bus arbitration used by a multiprocessing system with a single main bus is performed. The major performance parameters are delay time and the average number of active processors, called processing power. The bus arbitration methods are described using state and timing diagrams. Multiprocessor systems using these methods of arbitration are then modeled using Markov chains to enable the formulation of processing power. From processing power other...
Show moreA comparative analysis of two methods of bus arbitration used by a multiprocessing system with a single main bus is performed. The major performance parameters are delay time and the average number of active processors, called processing power. The bus arbitration methods are described using state and timing diagrams. Multiprocessor systems using these methods of arbitration are then modeled using Markov chains to enable the formulation of processing power. From processing power other performance parameters can be derived. A comparison is then made among the two bus arbitration methods based on the analytical results where processors access the bus at an equal rate. Simulations of multiprocessor systems using either of the two arbitration methods were performed to validate the analytical models for equal bus request rates. Simulations are also performed of a system of processors using the main bus at unequal rates.
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Date Issued
1986
PURL
http://purl.flvc.org/fcla/dt/14350
Subject Headings
Multiprocessors, System design
Format
Document (PDF)
PALSAM INPUT DATA FILE GENERATOR
Title
PALSAM INPUT DATA FILE GENERATOR.
Creator
ROBINSON, WILLIAM ROBERT, JR., Florida Atlantic University, Marcovitz, Alan B., College of Engineering and Computer Science, Department of Computer and Electrical Engineering and Computer Science
Abstract/Description
The capabilities and limitations of Programmable Array Logic devices (PALs) are presented and compared to other logic devices. PALs are field programmable devices and a program called PALSAM exists to assist the designer in programming PALs. The attributes and limitations of PALSAM are discussed. The PALSAM Input Data File Generator program was written to eliminate many of the limitations of PALSAM. The need for an algorithmic method of reducing a general logic expression to a minimal sum-of...
Show moreThe capabilities and limitations of Programmable Array Logic devices (PALs) are presented and compared to other logic devices. PALs are field programmable devices and a program called PALSAM exists to assist the designer in programming PALs. The attributes and limitations of PALSAM are discussed. The PALSAM Input Data File Generator program was written to eliminate many of the limitations of PALSAM. The need for an algorithmic method of reducing a general logic expression to a minimal sum-of-products form is demonstrated. Several algorithms are discussed. The Zissos, Duncan and Jones Algorithm, which claims to produce a minimal sum-of-products expression but is presented without proof by its authors, is disproved by example. A modification of this algorithm is presented without proof. When tested in the 276 possible cases involving up to three variables, this new algorithm always produced a minimal sum-of-products expression, while the original algorithm failed in six of these cases. Finally, the PALSAM Input Data File Generator program which uses the modified algorithm is presented and documented.
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Date Issued
1984
PURL
http://purl.flvc.org/fcla/dt/14199
Subject Headings
Programmable array logic, Microprocessors--Programming, Algorithms
Format
Document (PDF)