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Novel multiplexer-based architectures for full adder design

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Date Issued:
2000
Summary:
We propose five new Multiplexer-Based architectures for 1-bit full adder design. Using a 2-transistors multiplexer gate to implement the first architecture, we are able to produce a 12-transistor full adder cell, Comparing it to four different 10-transistors low-power full adder cells reported previously in literature, the new adder cell named MBA1-12T out performs all of them in power consumption and speed. By implementing those architectures using the 2-input CMOS multiplexer with pass-gates, five new high-performance full adder cells are obtained. Those new adder cells are tested along with the conventional 28-transistor CMOS adder cell. Testing results shows that the new adder cells have higher speed and lower power delay product values than the conventional 28-transistor CMOS adder cell.
Title: Novel multiplexer-based architectures for full adder design.
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Name(s): Al-Sheraidah, Abdulkarim K.
Florida Atlantic University, Degree grantor
Wang, Yuke, Thesis advisor
Type of Resource: text
Genre: Electronic Thesis Or Dissertation
Issuance: monographic
Date Issued: 2000
Publisher: Florida Atlantic University
Place of Publication: Boca Raton, Fla.
Physical Form: application/pdf
Extent: 74 p.
Language(s): English
Summary: We propose five new Multiplexer-Based architectures for 1-bit full adder design. Using a 2-transistors multiplexer gate to implement the first architecture, we are able to produce a 12-transistor full adder cell, Comparing it to four different 10-transistors low-power full adder cells reported previously in literature, the new adder cell named MBA1-12T out performs all of them in power consumption and speed. By implementing those architectures using the 2-input CMOS multiplexer with pass-gates, five new high-performance full adder cells are obtained. Those new adder cells are tested along with the conventional 28-transistor CMOS adder cell. Testing results shows that the new adder cells have higher speed and lower power delay product values than the conventional 28-transistor CMOS adder cell.
Identifier: 9780599813588 (isbn), 12667 (digitool), FADT12667 (IID), fau:9549 (fedora)
Collection: FAU Electronic Theses and Dissertations Collection
Note(s): College of Engineering and Computer Science
Thesis (M.A.S.)--Florida Atlantic University, 2000.
Subject(s): Metal oxide semiconductors, Complementary
Digital integrated circuits
Held by: Florida Atlantic University Libraries
Persistent Link to This Record: http://purl.flvc.org/fcla/dt/12667
Sublocation: Digital Library
Use and Reproduction: Copyright © is held by the author, with permission granted to Florida Atlantic University to digitize, archive and distribute this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder.
Use and Reproduction: http://rightsstatements.org/vocab/InC/1.0/
Host Institution: FAU
Is Part of Series: Florida Atlantic University Digital Library Collections.