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Dynamically reconfigurable power-aware, highly scalable multiplier with reusable and locally optimized structures

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Date Issued:
2005-06
Title: Dynamically reconfigurable power-aware, highly scalable multiplier with reusable and locally optimized structures.
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Name(s): Shankar, Ravi, creator
Florida Atlantic University, creator
Type of Resource: text
Genre: Patent
Date Issued: 2005-06
Extent: 27p.
Physical Description: PDF
Language(s): English
Identifier: 15796 (digitool), FADT15796 (IID), fau:7167 (fedora)
Note(s): PATENT STATUS: Pending. A large bit width multiplier with multiple copies of a core small bit width multiplier and ROM cells. The present invention provides a power system that trades off processing speed against power dissipation. The present invention reduces power dissipation to about half of the best industry implementation at about half the speed. Its power dissipation is 10% of another industry standard implementation at 1.5 times the speed. The present invention has a gate count that is about twice the gate count for these implementations.
Persistent Link to This Record: http://purl.flvc.org/fcla/dt/15796
Owner Institution: FAU
Has Part: Florida Atlantic University.
Has Part: Office of Technology Transfer.
Has Part: Patents.